Datasheet

PVIN
SW
PGND
L
V
OUT
LM20133
C
IN
C
OUT
LOOP1
LOOP2
LM20133, LM20133Q
SNVS526F –OCTOBER 2007–REVISED MARCH 2013 www.ti.com
PCB LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched
very fast. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin, to
the inductor then out to the output capacitor and load. The second loop starts from the output capacitor
ground, to the regulator PGND pins, to the inductor and then out to the load (see Figure 38). To minimize
both loop areas the input capacitor should be placed as close as possible to the PVIN pin. Grounding for
both the input and output capacitor should consist of a small localized top side plane that connects to PGND
and the die attach pad (DAP). The inductor should be placed as close as possible to the SW pin and output
capacitor.
2. Minimize the copper area of the switch node. Since the LM20133 has the SW pins on opposite sides of the
package it is recommended to via these pins down to the bottom or internal layer with 2 to 4 vias on each
SW pin. The SW pins should be directly connected with a trace that runs across the bottom of the package.
To minimize IR losses this trace should be no smaller that 50 mils wide, but no larger than 100 mils wide to
keep the copper area to a minimum. In general the SW pins should not be connected on the top layer since it
could block the ground return path for the power ground. The inductor should be placed as close as possible
to one of the SW pins to further minimize the copper area of the switch node.
3. Have a single point ground for all device analog grounds located under the DAP. The ground connections for
the compensation, feedback, and Soft-Start components should be connected together then routed to the
AGND pin of the device. The AGND pin should connect to PGND under the DAP. This prevents any
switched or load currents from flowing in the analog ground plane. If not properly handled poor grounding
can result in degraded load regulation or erratic switching behavior.
4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the
output resistor divider to FB pin should be as short as possible. This is most important when high value
resistors are used to set the output voltage. The feedback trace should be routed away from the SW pin and
inductor to avoid contaminating the feedback signal with switch noise.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure
feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide
the best output accuracy.
6. Provide adequate device heatsinking. Use as many vias as is possible to connect the DAP to the power
plane heatsink. For best results use a 4x4 via array with a minimum via diameter of 12 mils. See the Thermal
Considerations section to insure enough copper heatsinking area is used to keep the junction temperature
below 125°C.
Figure 38. Schematic of LM20133 Highlighting Layout Sensitive Nodes
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