Datasheet
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Comparison
- 4 Terminal Configuration and Functions
- 4.1 PGE QFP Package Pinout (144-Pin)
- 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
- 4.3 Terminal Functions
- 4.3.1 PGE Package
- 4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.1.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.1.3 Enhanced Capture Modules (eCAP)
- 4.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.1.6 General-Purpose Input / Output (GPIO)
- 4.3.1.7 Controller Area Network Controllers (DCAN)
- 4.3.1.8 Local Interconnect Network Interface Module (LIN)
- 4.3.1.9 Standard Serial Communication Interface (SCI)
- 4.3.1.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.1.11 Standard Serial Peripheral Interface (SPI)
- 4.3.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.1.13 Ethernet Controller
- 4.3.1.14 USB Host and Device Port Controller Interface
- 4.3.1.15 System Module Interface
- 4.3.1.16 Clock Inputs and Outputs
- 4.3.1.17 Test and Debug Modules Interface
- 4.3.1.18 Flash Supply and Test Pads
- 4.3.1.19 Supply for Core Logic: 1.2V nominal
- 4.3.1.20 Supply for I/O Cells: 3.3V nominal
- 4.3.1.21 Ground Reference for All Supplies Except VCCAD
- 4.3.2 ZWT Package
- 4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC)
- 4.3.2.2 Enhanced High-End Timer Modules (N2HET)
- 4.3.2.3 Enhanced Capture Modules (eCAP)
- 4.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
- 4.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)
- 4.3.2.6 General-Purpose Input / Output (GPIO)
- 4.3.2.7 Controller Area Network Controllers (DCAN)
- 4.3.2.8 Local Interconnect Network Interface Module (LIN)
- 4.3.2.9 Standard Serial Communication Interface (SCI)
- 4.3.2.10 Inter-Integrated Circuit Interface Module (I2C)
- 4.3.2.11 Standard Serial Peripheral Interface (SPI)
- 4.3.2.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
- 4.3.2.13 Ethernet Controller
- 4.3.2.14 USB Host and Device Port Controller Interface
- 4.3.2.15 External Memory Interface (EMIF)
- 4.3.2.16 System Module Interface
- 4.3.2.17 Clock Inputs and Outputs
- 4.3.2.18 Test and Debug Modules Interface
- 4.3.2.19 Flash Supply and Test Pads
- 4.3.2.20 Reserved
- 4.3.2.21 No Connects
- 4.3.2.22 Supply for Core Logic: 1.2V nominal
- 4.3.2.23 Supply for I/O Cells: 3.3V nominal
- 4.3.2.24 Ground Reference for All Supplies Except VCCAD
- 4.3.1 PGE Package
- 5 Specifications
- 5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Device Recommended Operating Conditions
- 5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains
- 5.6 Wait States Required
- 5.7 Power Consumption Over Recommended Operating Conditions
- 5.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions
- 5.9 Thermal Resistance Characteristics
- 5.10 Output Buffer Drive Strengths
- 5.11 Input Timings
- 5.12 Output Timings
- 5.13 Low-EMI Output Buffers
- 6 System Information and Electrical Specifications
- 6.1 Device Power Domains
- 6.2 Voltage Monitor Characteristics
- 6.3 Power Sequencing and Power On Reset
- 6.4 Warm Reset (nRST)
- 6.5 ARM Cortex-R4F CPU Information
- 6.6 Clocks
- 6.7 Clock Monitoring
- 6.8 Glitch Filters
- 6.9 Device Memory Map
- 6.10 Flash Memory
- 6.11 Tightly Coupled RAM Interface Module
- 6.12 Parity Protection for Accesses to Peripheral RAMs
- 6.13 On-Chip SRAM Initialization and Testing
- 6.14 External Memory Interface (EMIF)
- 6.15 Vectored Interrupt Manager
- 6.16 DMA Controller
- 6.17 Real Time Interrupt Module
- 6.18 Error Signaling Module
- 6.19 Reset / Abort / Error Sources
- 6.20 Digital Windowed Watchdog
- 6.21 Debug Subsystem
- 7 Peripheral Information and Electrical Specifications
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 7.1.1 ePWM Clocking and Reset
- 7.1.2 Synchronization of ePWMx Time Base Counters
- 7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
- 7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
- 7.1.5 ePWM Synchronization with External Devices
- 7.1.6 ePWM Trip Zones
- 7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
- 7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
- 7.2 Enhanced Capture Modules (eCAP)
- 7.3 Enhanced Quadrature Encoder (eQEP)
- 7.4 Multibuffered 12bit Analog-to-Digital Converter
- 7.5 General-Purpose Input/Output
- 7.6 Enhanced High-End Timer (N2HET)
- 7.7 Controller Area Network (DCAN)
- 7.8 Local Interconnect Network Interface (LIN)
- 7.9 Serial Communication Interface (SCI)
- 7.10 Inter-Integrated Circuit (I2C)
- 7.11 Multibuffered / Standard Serial Peripheral Interface
- 7.12 Ethernet Media Access Controller
- 7.13 Universal Serial Bus (USB) Host and Device Controllers
- 7.1 Enhanced Translator PWM Modules (ePWM)
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
- Important Notice
- 1518515_DS2.pdf
RM46L852
www.ti.com
SPNS185C –SEPTEMBER 2012–REVISED JUNE 2015
Table 4-2. PGE Enhanced High-End Timer Modules (N2HET) (continued)
Terminal Signal Reset Pull Pull Type Description
Type State
Signal Name 144
PGE
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 14 I/O Pulldown Programmable, Disable selected PWM
20 µA
(1)
outputs
GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/ 9 I/O Pulldown Programmable,
N2HET2 time input
EQEP2I 20 µA
capture or output
GIOA[6]/N2HET2[4]/EPWM1B 16
compare, or GPIO
GIOA[7]/N2HET2[6]/EPWM2A 22
Each terminal has a
suppression filter with a
N2HET1[1]/SPI4NENA/USB2.TXEN/ 23
programmable duration.
USB_FUNC.PUENO/N2HET2[8]/EQEP2A
N2HET1[3]/SPI4NCS[0]/USB2.SPEED/ 24
USB_FUNC.PUENON/N2HET2[10]/EQEP2B
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B 31
N2HET1[7]/USB2.PORTPOWER/USB_FUNC.GZO/ 33
N2HET2[14]/EPWM7B
N2HET1[9]/N2HET2[16]/USB2.SUSPEND/ 35
USB_FUNC.SUSPENDO/EPWM7A
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6
USB2.OVERCURRENT/USB_FUNC.VBUSI/
EPWM1SYNCO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/ 55 I/O Pullup Programmable, Disable selected PWM
EQEP1I/N2HET2_PIN_nDIS 20 µA
(1)
outputs
(1) The N2HETx_PIN_nDIS function is always available on this terminal. There is no mux control to select this function. The pull direction is
controlled by the function which is selected by the output mux control for this terminal.
4.3.1.3 Enhanced Capture Modules (eCAP)
Table 4-3. PGE Enhanced Capture Modules (eCAP)
(1)
Terminal Signal Reset Pull Pull Type Description
Type State
Signal Name 144
PGE
N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 I/O Pulldown Fixed 20 µA Enhanced Capture
Pullup Module 1 I/O
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2 51 Pullup Enhanced Capture
Module 2 I/O
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3 52 Enhanced Capture
Module 3 I/O
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ 96 Enhanced Capture
USB1.VP/ECAP4 Module 4 I/O
MIBSPI5NENA/MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ 97 Enhanced Capture
ECAP5 Module 5 I/O
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105 Enhanced Capture
USB1.RCV/ECAP6 Module 6 I/O
(1) These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.
Copyright © 2012–2015, Texas Instruments Incorporated Terminal Configuration and Functions 13
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