Datasheet

-IN
R
G
R
G
+IN
+V
S
V
OUT
REF
-V
S
1
2
3
4
8
7
6
5
Exposed
Thermal
DiePad
on
Underside
R
G
R
G
+IN
+V
S
V
OUT
REF
1
2
3
4
8
7
6
5
-IN
-V
S
INA826
SBOS562E –AUGUST 2011–REVISED APRIL 2013 www.ti.com
PIN CONFIGURATIONS
DGK PACKAGE
DRG PACKAGE
MSOP-8, SO-8
3-mm × 3-mm DFN-8
(TOP VIEW)
(TOP VIEW)
PIN DESCRIPTIONS
NAME NO. DESCRIPTION
–IN 1 Negative input
R
G
2 Gain setting pin. Place a gain resistor between pin 2 and pin 3.
R
G
3 Gain setting pin. Place a gain resistor between pin 2 and pin 3.
+IN 4 Positive input
–V
S
5 Negative supply
REF 6 Reference input. This pin must be driven by low impedance.
V
OUT
7 Output
+V
S
8 Positive supply
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