Datasheet

INA332, INA2332
12
SBOS216B
www.ti.com
OFFSET VOLTAGE ERROR CALCULATION
The offset voltage (V
OS
) of the INA332AIDGK is specified at
a maximum of 500µV with a +5V power supply and the
common-mode voltage at V
S
/2. Additional specifications for
power-supply rejection and common-mode rejection are pro-
vided to allow the user to easily calculate worst-case ex-
pected offset under the conditions of a given application.
Power-Supply Rejection Ratio (PSRR) is specified in µV/V.
For the INA332, worst case PSRR is 200µV/V, which means
for each volt of change in power supply, the offset may shift
up to 200µV. Common-Mode Rejection Ratio (CMRR) is
specified in dB, which can be converted to µV/V using the
following equation:
CMRR (in µV/V) = 10
[(CMRR in dB)/–20]
• 10
6
For the INA332, the worst case CMRR over the specified
common-mode range is 60dB (at G = 25) or about 30µV/V
This means that for every volt of change in common-mode,
the offset will shift less than 30µV.
These numbers can be used to calculate excursions from the
specified offset voltage under different application condi-
tions. For example, an application might configure the ampli-
fier with a 3.3V supply with 1V common-mode. This configu-
ration varies from the specified configuration, representing a
1.7V variation in power supply (5V in the offset specification
versus 3.3V in the application) and a 0.65V variation in
common-mode voltage from the specified V
S
/2.
Calculation of the worst-case expected offset would be as
follows:
Adjusted V
OS
= Maximum specified V
OS
+
(power-supply variation) • PSRR +
(common-mode variation) • CMRR
V
OS
= 0.5mV + (1.7V • 200µV) + (0.65V • 30µV)
= ±0.860mV
However, the typical value will be smaller, as seen in the
Typical Characteristics.
FEEDBACK CAPACITOR IMPROVES RESPONSE
For optimum settling time and stability with high-impedance
feedback networks, it may be necessary to add a feedback
capacitor across the feedback resistor, R
F
, as shown in
Figure 8. This capacitor compensates for the zero created by
the feedback network impedance and the INA332’s RG-pin
input capacitance (and any parasitic layout capacitance).
The effect becomes more significant with higher impedance
networks. Also, R
X
and C
L
can be added to reduce high-
frequency noise.
It is suggested that a variable capacitor be used for the
feedback capacitor since input capacitance may vary be-
tween instrumentation amplifiers, and layout capacitance is
difficult to determine. For the circuit shown in Figure 8, the
value of the variable feedback capacitor should be chosen by
the following equation:
R
IN
• C
IN
= R
F
• C
F
Where C
IN
is equal to the INA332’s RG-pin input capacitance
(typically 3pF) plus the layout capacitance. The capacitor can
be varied until optimum performance is obtained.
FIGURE 8. Feedback Capacitor Improves Dynamic Perfor-
mance.
INA332
V+
V
OUT
R
IN
R
IN
• C
IN
= R
F
• C
F
R
F
R
X
C
L
C
IN
Where C
IN
is equal to the INA332’s input capacitance
(approximately 3pF) plus any parastic layout capacitance.
5
3
2
8
7
6
4
1
Shutdown
RG
V
IN
–
V–
V
IN
+
REF
C
F