Datasheet

SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
t
(BUF)
S
S
P
P
INA226
SBOS547 –JUNE 2011 www.ti.com
High-Speed I
2
C Mode
When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up devices. The master generates
a start condition followed by a valid serial byte containing High-Speed (HS) master code 00001XXX. This
transmission is made in fast (400kHz) or standard (100kHz) (F/S) mode at no more than 400kHz. The INA226
does not acknowledge the HS master code, but does recognize it and switches its internal filters to support
3.4MHz operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 3.4MHz are allowed. Instead of using a stop condition, repeated start conditions should be used to
secure the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the
INA226 to support the F/S mode.
Figure 28. Bus Timing Diagram
Bus Timing Diagram Definitions
FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNITS
SCL operating frequency f
(SCL)
0.001 0.4 0.001 3.4 MHz
Bus free time between stop and start
t
(BUF)
600 160 ns
conditions
Hold time after repeated START condition.
t
(HDSTA)
100 100 ns
After this period, the first clock is generated.
Repeated start condition setup time t
(SUSTA)
100 100 ns
STOP condition setup time t
(SUSTO)
100 100 ns
Data hold time t
(HDDAT)
0 0 ns
Data setup time t
(SUDAT)
100 10 ns
SCL clock low period t
(LOW)
1300 160 ns
SCL clock high period t
(HIGH)
600 60 ns
Clock/data fall time t
F
300 160 ns
Clock/data rise time t
R
300 160 ns
Clock/data rise time for SCLK ≤ 100kHz t
R
1000 ns
26 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): INA226