Datasheet
48REN
47
V
DD
PR0
46
V
SS
PR0
45
V
DD
PR1
44
V
SS
PR1
43RRFB
42RIN-
41RIN+
40
V
SS
IR
39
V
DD
IR
38
V
SS
R1
37
V
DD
R1
13
14
15
16
17
18
19
20
21
22
23
24
ROUT[15]
ROUT[14]
ROUT[13]
ROUT[12]
LOCK
RCLK
V
SS
OR2
V
DD
OR2
ROUT[11]
ROUT[10]
ROUT[9]
ROUT[8]
12
ROUT[16]
11
ROUT[17]
10
ROUT[18]
9
ROUT[19]
8
V
SS
OR3
7
V
DD
OR3
6
ROUT[20]
5
ROUT[21]
4
ROUT[22]
3
ROUT[23]
2
RESRVD
1
RPWDNB
25
26
27
28
29
30
31
32
33
34
35
36
ROUT[7]
ROUT[6]
ROUT[5]
ROUT[4]
V
SS
OR1
V
DD
OR1
ROUT[3]
ROUT[2]
ROUT[1]
ROUT[0]
V
SS
R0
V
DD
R0
PTO GROUP 3
PTO GROUP 1
PTO GROUP 2
DS99R104
48 PIN WQFN
48 PIN TQFP
DS99R103, DS99R104
SNLS241D –MARCH 2007–REVISED APRIL 2013
www.ti.com
DS99R104 Pin Diagram
Top View
Figure 18. Deserializer - DS99R104
See Package Numbers NJU0048D (WQFN) and PFB0048A (TQFP)
DS99R104 Deserializer Pin Descriptions
Pin
Pin Name I/O Description
No.
LVCMOS PARALLEL INTERFACE PINS
25-28, ROUT[7:0] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 1
31-34
13-16, ROUT[15:8] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 2
21-24
3-6, 9- ROUT[23:16] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 3
12
18 RCLK LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
43 RRFB LVCMOS_I Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
48 REN LVCMOS_I Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
1 RPWDNB LVCMOS_I Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
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