Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - deserialisers Channel Link III (LVCMOS) WQFN 48

DS92LX2121, DS92LX2122

www.ti.com

SNLS330I –MAY 2010–REVISED APRIL 2013

DS92LX2121/DS92LX2122 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control

Serializer and Deserializer

Check for Samples: DS92LX2121, DS92LX2122

FEATURES

APPLICATIONS

• General

• Industrial Displays, Touch Screens

– Up to 1050 Mbits/sec Data Throughput • Medical Imaging

– 10 MHz to 50 MHz Input Clock Support

DESCRIPTION

– Supports 18-bit Color Depth (RGB666 + HS,

The DS92LX2121/DS92LX2122 chipset offers a

VS, DE)

Channel Link III interface with a high-speed forward

– Embedded Clock with DC Balanced Coding

channel and a full-duplex control channel for data

to Support AC-Coupled Interconnects

transmission over a single differential pair. The

DS92LX2121/DS92LX2122 incorporates differential

– Capable to Drive up to 10 Meters Shielded

signaling on both the high-speed and bi-directional

Twisted-Pair

back channel control data paths. The Serializer/

– Bi-Directional Control Interface Channel

Deserializer pair is targeted for direct connections

with I

C Support

between graphics host controller and displays

– I

C Interface for Device Configuration.

modules. This chipset is ideally suited for driving

Single-Pin ID Addressing

video data to displays requiring 18-bit color depth

(RGB666 + HS, VS, and DE) along with a bi-

– Up to 4 GPI on DES and GPO on SER

directional back channel control bus. The primary

– AT-SPEED BIST Diagnosis Feature to

transport converts 21 bit data over a single high-

Validate Link Integrity

speed serial stream, along with a separate low

– Individual Power-Down Controls for both

latency bi-directional back channel transport that

accepts control information from an I2C port. Using

SER and DES

TI’s embedded clock technology allows transparent

– User-Selectable Clock Edge for Parallel

full-duplex communication over a single differential

Data on both SER and DES

pair, carrying asymmetrical bi-directional back

– Integrated Termination Resistors

channel control information in both directions. This

single serial stream simplifies transferring a wide data

– 1.8V- or 3.3V-Compatible Parallel Bus

bus over PCB traces and cable by eliminating the

Interface

skew problems between parallel data and clock

– Single Power Supply at 1.8V

paths. This significantly saves system cost by

– IEC 61000–4–2 ESD Compliant

narrowing data paths that in turn cable width,

connector size and pins.

– Temperature Range −40°C to +85°C

• DESERIALIZER — DS92LX2122

In addition, the Deserializer provides input

equalization to compensate for loss from the media

– No Reference Clock Required on

over longer distances. Internal DC balanced

Deserializer

encoding/decoding is used to support AC-Coupled

– Programmable Receive Equalization

interconnects.

– LOCK Output Reporting Pin to Ensure

A sleep function provides a power-savings mode

– EMI/EMC Mitigation

when the high speed forward channel and embedded

– Programmable Spread Spectrum (SSCG)

bi-directional control channel are not needed.

Outputs

The Serializer is offered in a 40-pin lead in WQFN

– Receiver Output Drive Strength Control

and Deserializer is offered in a 48-pin WQFN

(RDS)

packages.

– Receiver Staggered Outputs

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (42 pages)

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DS92LX2121, DS92LX2122 www.ti.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.
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DS92LX2121, DS92LX2122 www.ti.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com DS92LX2121 Serializer PIN DESCRIPTIONS (continued) Pin Name Pin No. I/O, Type Description Power down Mode Input Pin. PDB = H, Transmitter is enabled and is ON. PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in the SLEEP state, the PLL is shutdown, and IDD is minimized. CONTROL AND CONFIGURATION PDB 13 Input, LVCMOS w/ pull down RES 10, 11 Input, LVCMOS w/ pull down Reserved.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 DS92LX2122 Deserializer PIN DESCRIPTIONS Pin Name Pin No. I/O, Type Description LVCMOS PARALLEL INTERFACE ROUT[20:0] PCLK 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28 Outputs, LVCMOS Parallel data outputs. 4 Output, LVCMOS Pixel Clock Output Pin. Strobe edge set by RFB configuration. In SLEEP, outputs are controlled by the OSS_SEL.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com DS92LX2122 Deserializer PIN DESCRIPTIONS (continued) Pin Name Pin No. I/O, Type Description POWER AND GROUND 3 Digital Power SSCG Power, 1.8V ±5% Power supply must be connect regardless if SSCG function is in operation 29, 20, 7 Digital Power TTL Output Buffer Power, The single-ended outputs and control input are powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 Recommended Operating Conditions (continued) Min Nom Max Units VDDn (1.8 V) 25 mVP-P VDDIO (1.8 V) 25 mVP-P 50 mVP-P Supply Noise (1) VDDIO (3.3 V) Operating Free Air Temperature (TA) -40 Input Clock Rate (1) 25 10 85 °C 50 MHz Supply noise testing was done with minimum capacitors (as shown on Figures 35, 36) on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com Serializer Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 Serializer Electrical Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Deserializer (Rx) VDDn Supply Current (includes load current) IDDR IDDIOR IDDRZ Min Max 96 VDDn = 1.89V CL = 8pF WORST CASE Pattern (See Figure 6) PCLK = 50 MHz SSCG[3:0] = ON Default Registers 60 VDDn = 1.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 Serializer Electrical Characteristics Deserializer Switching Characteristics(1)(2)(3) (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com Bi-Directional Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (Figure 5) (continued) Over recommended operating supply and temperature ranges unless otherwise specified.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant (continued) Symbol VOL Parameter Conditions Low Level Output Voltage Max Units SCL and SDA VDDIO = 3.0V IOL = 1.5 mA Min Typ 0.36 V SCL and SDA VDDIO = 1.71V IOL = 1 mA 0.36 V AC Timing Diagrams and Test Circuits Device Pin Name Signal Pattern T PCLK ODD DIN/ROUT EVEN DIN/ROUT Figure 6.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com DOUT- Single Ended V V OD V OD+ ODV DOUT+ | OS 0V Differential V OD+ 0V (DOUT+)-(DOUT-) V OD- Figure 10. Serializer VOD DC Diagram RIN+ VCM = 1.2V RIN+ VT H VID VTL VIN VID VIN RIN- RIN- GND Figure 11. Low-Voltage Differential VTH/VTL Definition Diagram 80% VDD 80% PCLK 20% 20% 0V tCLKT tCLKT Figure 12.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 PDB (3.3V I/O) 2.0V PCLK tPLD TRI-STATE DOUT± TRI-STATE Output Active DIN/HS/VS SYMBOL N SYMBOL N+1 SYMBOL N+2 | | Figure 14. Serializer Data Lock Time SYMBOL N+3 tSD SYMBOL N | | SYMBOL N-1 | | DOUT+- SYMBOL N-2 | | SYMBOL N-3 | | SYMBOL N-4 | | | PCLK Figure 15. Serializer Delay 2.0V PDB (3.3V I/O) | | t DDLT RIN ± LOCK | TRI - STATE Figure 16.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com tROS VDDIO VDDIO/2 ROUT/HS/VS VDDIO/2 0V tROH VDDIO PCLK VDDIO/2 0V Figure 19. Deserializer Output Setup/Hold Times Frequency FPCLK+ fdev fdev (max) FPCLK FPCLK- fdev (min) Time 1 / fmod Figure 20. Spread Spectrum Clock Output Profile 2 JITTER TRANSFER (dB) 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 1.0E+04 1.0E+05 1.0E+06 1.0E+07 MODULATION FREQUENCY (Hz) Figure 21.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 Table 1. DS92LX2121 Control Registers Addr (Hex) 0 Name Bits Field R/W Default 7:1 DEVICE ID RW 0x58 SER ID RW 0 0: Device ID is from CAD 1: Register I2C Device ID overrides CAD 0 Reserved. Standby mode control. Retains control register data. Supported only when M/S = 0 0: Enabled. Low-current Standby mode with wake-up capability. Suspends all clocks and functions. 1: Disabled.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com Table 1. DS92LX2121 Control Registers (continued) Addr (Hex) C Name Bits Field R/W Reserved 7:3 RESERVED PCLK Detect 2 PCLK DETECT R Default Description 0 Reserved. 0 1: Valid PCLK detected 0: Valid PCLK not detected Reserved 1 RESERVED Cable Link Detect Status Reserved. 0 LINK DETECT D Reserved 7:0 RESERVED Reserved. E Reserved 7:0 RESERVED Reserved. F Reserved 7:0 RESERVED Reserved.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 Table 2. DS92LX2122 Control Registers (continued) Addr (Hex) Name Bits Field Reserved 7:6 RESERVED Auto Clock 5 AUTO_CLOCK OSS Select 4 OSS_SEL R/W Default 0 Reserved.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com Table 2. DS92LX2122 Control Registers (continued) Addr (Hex) Name Bits Reserved 7 SCL Prescale 6 Remote NACK Remote NACK 7 8 ID[0] Index 9 ID[1] Index A ID[2] Index B ID[3] Index C ID[4] Index D ID[5] Index E ID[6] Index F ID[7] Index 10 20 SER ID ID[0] Match 11 ID[1] Match 12 ID[2] Match 13 ID[3] Match 14 ID[4] Match Field R/W Default Description RESERVED Reserved.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 Table 2. DS92LX2122 Control Registers (continued) Addr (Hex) Name 15 ID[5] Match 16 Bits ID[6] Match Field 7:1 ID[5] MATCH 0 RESERVED 7:1 ID[6] MATCH 0 RESERVED 7:1 ID[7] MATCH 0 RESERVED R/W Default RW 0 Alias to match Device ID slv_id5 [7:1] 0 Reserved 0 Alias to match Device ID slv_id6 [7:1] 0 Reserved. 0 Alias to match Device ID slv_id [7:1] 0 Reserved.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS92LX2121 / DS92LX2122 Channel Link III chipset is intended for camera applications. The Serializer/ Deserializer chipset operates from a 10 MHz to 50 MHz pixel clock frequency. The DS92LX2121 transforms a 21-bit wide parallel LVCMOS data bus along with a bi-directional back channel control bus into a single highspeed differential pair.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 Bus Activity: Master SDA Line Register Address Slave Address 7-bit Address S Stop Start To start any data transfer, the DS92LX2121 / DS92LX2122 must be configured in the proper I2C mode. Each device can function as an I2C slave proxy or master proxy depending on the mode determined by M/S pin. The Ser/Des interface acts as a virtual bridge between the host device and the remote device.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com 1.8V 10k VDDIO CAD 4.7k 4.7k RCAD HOST SCL SCL SDA SDA SER or DES To other Devices Figure 28. Serial Control Bus Connection SLAVE CLOCK STRETCHING In order to communicate and synchronize with remote devices on the I2C bus through the bi-directional control channel, slave clock stretching must be supported by the I2C master controller/host device.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 CAMERA MODE OPERATION In Camera mode, I2C transactions originate from the Deserializer from the host controller. The I2C slave core in the Deserializer will detect if a transaction is intended for the Serializer or a slave at the Serializer. Commands are sent over the bi-directional control channel to initiate the transactions. The Serializer will receive the command and generate an I2C transaction on its local I2C bus.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com SYNCHRONIZING MULTIPLE LINKS For applications requiring synchronization across multiple links, it is recommended to utilize the General Purpose Input/ Output (GPI/GPO) pins to transmit control signals to synchronize slave peripherals together. To synchronize the peripherals properly, the system controller needs to provide a sync signal output. Note this form of synchronization timing relationship has a non-deterministic latency.
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DS92LX2121, DS92LX2122 www.ti.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com Wait 10 ms for Deserializer to acquire lock and then monitor the LOCK pin transition from LOW to HIGH. At this point, AT SPEED BIST is operational and the BIST process has begun. The Serializer will start transfer of an internally generated PRBS data pattern through the high speed serial link. This pattern traverses across the interconnecting link to the Deserializer.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 Any PASS result will remain unless it is changed by a new BIST session or cleared by asserting and releasing PDB. The default state of PASS after a PDB toggle is HIGH. It is important to note that AT SPEED BIST will only determine if there is an issue on the link that is not related to the clock and data recovery of the link (whose status is flagged with LOCK pin). LVCMOS VDDIO OPTION 1.8V or 3.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com EMI REDUCTION Des - Receiver Staggered Output The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 TYPICAL APPLICATION CONNECTION Figure 35 shows a typical connection of the DS92LX2121 Serializer. DS92LX2121 (SER) VDDIO VDDIO C12 FB1 C8 1.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com Figure 36 shows a typical connection of the DS92LX2122 Deserializer. DS92LX2122 (DES) 1.
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 TRANSMISSION MEDIA The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment. The interconnect for Channel Link III interface should present a differential impedance of 100 Ohms.
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DS92LX2121, DS92LX2122 SNLS330I – MAY 2010 – REVISED APRIL 2013 www.ti.com INTERCONNECT GUIDELINES For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008) and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035).
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DS92LX2121, DS92LX2122 www.ti.com SNLS330I – MAY 2010 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision H (April 2013) to Revision I • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS92LX2121SQ/NOPB WQFN RTA 40 DS92LX2121SQE/NOPB WQFN RTA DS92LX2121SQX/NOPB WQFN RTA DS92LX2122SQ/NOPB WQFN DS92LX2122SQE/NOPB DS92LX2122SQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LX2121SQ/NOPB WQFN RTA 40 1000 367.0 367.0 38.0 DS92LX2121SQE/NOPB WQFN RTA 40 250 213.0 191.0 55.0 DS92LX2121SQX/NOPB WQFN RTA 40 2500 367.0 367.0 38.0 DS92LX2122SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS92LX2122SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.
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MECHANICAL DATA RTA0040A SQA40A (Rev B) www.ti.
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