Datasheet

37
38
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44
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48
1 2 3 4 5 6 7 8 9
10 11 12
24
23
22
21
20
19
18
17
16
15
14
13
36 35 34 33 32 31 30 29 28 27 26 25
DS92LV2421
TOP VIEW
DAP = GND
DI21
DI20
DI18
DI17
DI14
DI13
DI11
DI10
CONFIG[1]
VDDP
RES1
VDDHS
DOUT+
PDB
De-Emph
VODSEL
DI12
DI15
DI16
DI19 RES0
RES2
DOUT-
VDDTX
DI22
CI2
CLKIN
CONFIG[0]
DI23
DI8 DI7
DI6 DI5 BISTEN
VDDIO
DI4
DI3
DI2 DI1 DI9
VDDL
SCL
RFB
DI0
SDA
CI3 CI1
ID[x]
RIN-
DS92LV2422 ± DESERIALIZER
RIN+
Clock and
Data
Recovery
Timing and
Control
LOCK
CLKOUT
SSCG
Output Latch
Serial to Parallel
DC Balance Decoder
PASS
DO[23:0]
CO1/DE
CO2/HS
CO3/VS
Error
Detector
PDB
BISTEN
CMF
SCL
SCA
ID[x]
STRAP INPUT
LF_MODE
OS_CLKOUT
OS_DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
STRAP INPUT
OP_LOW
EQ
ROUT-
ROUT+
DS92LV2421, DS92LV2422
www.ti.com SNLS321B –MAY 2010–REVISED APRIL 2013
DS92LV2421 Pin Diagram
Figure 1. Top View 48-pin WQFN
See Package Number RHS0048A
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Product Folder Links: DS92LV2421 DS92LV2422