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DS92LV090A

www.ti.com

SNLS025D –APRIL 2000–REVISED APRIL 2013

DS92LV090A 9 Channel Bus LVDS Transceiver

Check for Samples: DS92LV090A

FEATURES

DESCRIPTION

The DS92LV090A is one in a series of Bus LVDS

• Bus LVDS Signaling

transceivers designed specifically for the high speed,

• 3.2 Nanosecond Propagation Delay Max

low power proprietary backplane or cable interfaces.

• Chip to Chip Skew ±800ps

The device operates from a single 3.3V power supply

and includes nine differential line drivers and nine

• Low Power CMOS Design

receivers. To minimize bus loading, the driver outputs

• High Signaling Rate Capability (Above 100

and receiver inputs are internally connected. The

Mbps)

separate I/O of the logic side allows for loop back

• 0.1V to 2.3V Common Mode Range for V

support. The device also features a flow through pin

200mV

out which allows easy PCB routing for short stubs

between its pins and the connector.

• ±100 mV Receiver Sensitivity

The driver translates 3V TTL levels (single-ended) to

• Supports Open and Terminated Failsafe on

differential Bus LVDS (BLVDS) output levels. This

Port Pins

allows for high speed operation, while consuming

• 3.3V Operation

minimal power with reduced EMI. In addition, the

• Glitch Free Power Up/Down (Driver & Receiver

differential signaling provides common mode noise

Disabled)

rejection of ±1V.

• Light Bus Loading (5 pF Typical) per Bus

The receiver threshold is less than ±100 mV over a

LVDS Load

±1V common mode range and translates the

differential Bus LVDS to standard (TTL/CMOS)

• Designed for Double Termination Applications

levels. (See Applications Information Section for more

• Balanced Output Impedance

details.)

• Product Offered in 64 Pin LQFP Package

• High Impedance Bus Pins on Power off (V

0V)

• Driver Channel to Channel Skew (Same

Device) 230ps Typical

• Receiver Channel to Channel Skew (Same

Device) 370ps Typical

Simplified Functional Diagram

Figure 1.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
DS92LV090A www.ti.com SNLS025D – APRIL 2000 – REVISED APRIL 2013 DS92LV090A 9 Channel Bus LVDS Transceiver Check for Samples: DS92LV090A FEATURES DESCRIPTION • • • • • The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers.
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DS92LV090A SNLS025D – APRIL 2000 – REVISED APRIL 2013 www.ti.com Connection Diagram Figure 2. Top View Package Number PM0064 PIN DESCRIPTIONS Pin Name Pin # Input/Output Descriptions DO+/RI+ 27, 31, 35, 37, 41, 45, 47, 51, 55 I/O True Bus LVDS Driver Outputs and Receiver Inputs. DO−/RI− 26, 30, 34, 36, 40, 44, 46, 50, 54 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs. DIN 2, 6, 12, 18, 20, 22, 58, 60, 62 I TTL Driver Input.
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DS92LV090A www.ti.com Absolute Maximum Ratings SNLS025D – APRIL 2000 – REVISED APRIL 2013 (1) (2) (3) Supply Voltage (VCC) 4.0V Enable Input Voltage (DE, RE) −0.3V to (VCC +0.3V) Driver Input Voltage (DIN) −0.3V to (VCC +0.3V) Receiver Output Voltage (ROUT) −0.3V to (VCC +0.3V) −0.3V to +3.9V Bus Pin Voltage (DO/RI±) ESD (HBM 1.5 kΩ, 100 pF) >4.5 kV Driver Short Circuit Duration momentary Receiver Short Circuit Duration momentary Maximum Package Power Dissipation at 25°C LQFP 1.
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DS92LV090A SNLS025D – APRIL 2000 – REVISED APRIL 2013 www.ti.
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DS92LV090A www.ti.com SNLS025D – APRIL 2000 – REVISED APRIL 2013 AC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified Symbol Parameter (1) Conditions Min Typ Max Units RL = 27Ω, Figure 4, Figure 5, CL = 10 pF 0.6 1.4 2.2 ns 0.6 1.4 2.2 ns DIFFERENTIAL DRIVER TIMING REQUIREMENTS Differential Prop. Delay High to Low (2) tPLHD Differential Prop.
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DS92LV090A SNLS025D – APRIL 2000 – REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION General application guidelines and hints may be found in the following application notes: AN-808 (SNLA028), AN-903 (SNLA034), AN-971 (SNLA165), AN-977 (SNLA166), and AN-1108 (SNLA008). There are a few common practices which should be implied when designing PCB for Bus LVDS signaling. Recommended practices are: • Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals).
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DS92LV090A www.ti.com SNLS025D – APRIL 2000 – REVISED APRIL 2013 Test Circuits and Timing Waveforms Figure 3. Differential Driver DC Test Circuit Figure 4. Differential Driver Propagation Delay and Transition Time Test Circuit Figure 5.
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DS92LV090A SNLS025D – APRIL 2000 – REVISED APRIL 2013 www.ti.com Figure 6. Driver TRI-STATE Delay Test Circuit Figure 7. Driver TRI-STATE Delay Waveforms Figure 8. Receiver Propagation Delay and Transition Time Test Circuit Figure 9.
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DS92LV090A www.ti.com SNLS025D – APRIL 2000 – REVISED APRIL 2013 Figure 10. Receiver TRI-STATE Delay Test Circuit Figure 11. Receiver TRI-STATE Delay Waveforms Typical Bus Application Configurations Figure 12. Bi-Directional Half-Duplex Point-to-Point Applications Figure 13.
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DS92LV090A SNLS025D – APRIL 2000 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Nov-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS92LV090ATVEHX/NOP B Package Package Pins Type Drawing LQFP PM 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 12.35 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.35 2.2 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device DS92LV090ATVEHX/NOP B Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LQFP PM 64 1000 367.0 367.0 45.
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MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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