Datasheet

PCLK
IN
PCLK
OUT
HS/VS/DE
IN
HS/VS/DE
OUT
Latency
Pulses 1 or 2
PCLKs wide
Filetered OUT
DS90UR905Q, DS90UR906Q
SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013 www.ti.com
Table 2. DS90UR906Q Des Modes
CONFIG1 CONFIG0 Mode Ser Device
L L Normal Mode, Control Signal Filter disabled DS90UR905Q
L H Normal Mode, Control Signal Filter enabled DS90UR905Q
H L Backwards Compatible GEN2 DS90UR241
H H Backwards Compatible GEN1 DS90C241
VIDEO CONTROL SIGNAL FILTER — Ser and Des
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3
PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 20.
Figure 20. Video Control Signal Filter Waveform
SERIALIZER FUNCTIONAL DESCRIPTION
The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal
generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or
through the optional serial control bus. The Ser features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning and also the FPD-Link II data coding that
provides randomization, scrambling, and DC Balanacing of the video data. The Ser includes multiple features to
reduce EMI associated with display data transmission. This includes the randomization and scrambling of the
data and also the system spread spectrum PCLK support. The Ser features power saving features with a sleep
mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.
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