Datasheet

DS90UR905Q, DS90UR906Q

SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013

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DS90UR906Q Deserializer Pin Functions

(1)

(continued)

Pin Name Pin # I/O, Type Description

FPD-Link II Serial Interface

RIN+ 49 I, LVDS True Input. The input must be AC Coupled with a 100 nF capacitor.

RIN- 50 I, LVDS Inverting Input. The input must be AC Coupled with a 100 nF capacitor.

CMF 51 I, Analog Common-Mode Filter

VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver

common mode noise immunity. Recommended value is 0.1μF or higher.

CMLOUTP 52 O, LVDS Test Monitor Pin — EQ Waveform

NC or connect to test point. Requires Serial Bus Control to enable.

CMLOUTN 53 O, LVDS Test Monitor Pin — EQ Waveform

NC or connect to test point. Requires Serial Bus Control to enable.

Power and Ground

(2)

VDDL 29 Power Logic Power, 1.8 V ±5%

VDDIR 48 Power Input Power, 1.8 V ±5%

VDDR 43, 55 Power RX High Speed Logic Power, 1.8 V ±5%

VDDSC 4, 58 Power SSCG Power, 1.8 V ±5%

VDDPR 57 Power PLL Power, 1.8 V ±5%

VDDCMLO 54 Power RX High Speed Logic Power, 1.8 V ±5%

VDDIO 13, 24, 38 Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (V

DDIO

)

GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN

package. Connected to the ground plane (GND) with at least 9 vias.

(2) The VDD (V

DDn

and V

DDIO

) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on

the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.

Product Folder Links: DS90UR905Q DS90UR906Q