Datasheet

DS90UR905Q, DS90UR906Q
www.ti.com SNLS313G –SEPTEMBER 2009–REVISED APRIL 2013
Table 5. Receiver Equalization Configuration Table (continued)
INPUTS
Effect
EQ3 EQ2 EQ1 EQ0
L H H H ~6 dB
H L L H ~7.5 dB
H L H H ~9 dB
H H L H ~10.5 dB
H H H H ~12 dB
X X X L OFF*
* Default Setting is EQ = Off
EMI Reduction Features
Des — Output Slew (OS_PCLK/DATA)
The parallel bus outputs (RGB[7:0], VS, HS, DE and PCLK) of the Des feature a selectable output slew. The
DATA ((RGB[7:0], VS, HS, DE) are controlled by strap pin or register bit OS_DATA. The PCLK is controlled by
strap pin or register bit OS_PCLK. When the OS_PCLK/DATA = HIGH, the maximum slew rate is selected.
When the OS_PCLK/DATA = LOW, the minimum slew rate is selected. Use the higher slew rate setting when
driving longer traces or a heavier capacitive load.
Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1µF capacitor may be connected to this pin to Ground.
Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.0% (4% total) at up
to 35kHz modulations nominally are available. See Table 6. This feature may be controlled by external STRAP
pins or by register.
Table 6. SSCG Configuration (LF_MODE = L) — Des Output
SSC[3:0] Inputs Result
LF_MODE = L (20 - 65 MHz)
SSC3 SSC2 SSC1 SSC0 fdev (%) fmod (kHz)
L L L L Off Off
L L L H ±0.5
L L H L ±1.0
PCLK/2168
L L H H ±1.5
L H L L ±2.0
L H L H ±0.5
L H H L ±1.0
PCLK/1300
L H H H ±1.5
H L L L ±2.0
H L L H ±0.5
H L H L ±1.0
PCLK/868
H L H H ±1.5
H H L L ±2.0
H H L H ±0.5
H H H L ±1.0 PCLK/650
H H H H ±1.5
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