Datasheet

DS90UR124Q, DS90UR241Q
SNLS231N –SEPTEMBER 2006–REVISED MARCH 2013 www.ti.com
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
LLHT
LVDS Low-to-High Transition Time R
L
= 100Ω, VODSEL = L, 245 550 ps
C
L
= 10 pF to GND, Figure 3
t
LHLT
LVDS High-to-Low Transition Time 264 550 ps
t
DIS
D
IN
(0:23) Setup to TCLK R
L
= 100Ω, C
L
= 10 pF to GND
(1)
4 ns
Figure 5
(2)
t
DIH
D
IN
(0:23) Hold from TCLK 4 ns
t
HZD
D
OUT
± HIGH to TRI-STATE Delay R
L
= 100Ω, 10 15 ns
C
L
= 10 pF to GND
(3)
t
LZD
D
OUT
± LOW to TRI-STATE Delay 10 15 ns
Figure 6
t
ZHD
D
OUT
± TRI-STATE to HIGH Delay 75 150 ns
t
ZLD
D
OUT
± TRI-STATE to LOW Delay 75 150 ns
t
PLD
Serializer PLL Lock Time R
L
= 100Ω 10 ms
t
SD
Serializer Delay R
L
= 100Ω, PRE = OFF,
RAOFF = L, TRFB = H, 3.5T+2 3.5T+10 ns
Figure 8
(4)
R
L
= 100Ω, PRE = OFF,
RAOFF = L, TRFB = L, 3.5T+2 3.5T+10 ns
Figure 8
(4)
TxOUT_E_O TxOUT_Eye_Opening. 5 MHz–43 MHz,
TxOUT_E_O centered on (tBIT/)2 R
L
= 100Ω, C
L
= 10 pF to GND,
0.76 0.84 UI
RANDOM pattern
(5)(6)(7)
Figure 9
(1) Specification is guaranteed by characterization and is not tested in production.
(2) Figure 5, Figure 15 and Figure 16 show a rising edge data strobe (TCLK IN/RCLK OUT).
(3) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
(4) Figure 1, Figure 2, Figure 8, Figure 12 and Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
(5) t
JIT
(@BER of 10e-9) specifies the allowable jitter on TCLK. t
JIT
not included in TxOUT_E_O parameter.
(6) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
(7) TxOUT_E_O is affected by pre-emphasis value.
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