Datasheet
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
DS9UB903Q
Serializer
40-Pin WQFN
(Top View)
V
DDIO
DIN[8]
DIN[9]
V
DDD
DIN[10]
DIN[12]
DIN[13]
DIN[14]
DIN[15]
V
DDT
V
DDPLL
PDB
RES
MODE
DOUT-
GPO[1]
GPO[0]
V
DDCML
DOUT+
GPO[2]
GPO[3]
DIN[0]
DIN[1]
DIN[2]
DIN[3]
DIN[4]
DIN[5]
DIN[6]
DIN[7]
RES
ID[x]
SDA
SCL
DIN[20]
PCLK
DIN[19]
DIN[18]
DIN[17]
DIN[16]
DIN[11]
DAP = GND
DS90UB903Q, DS90UB904Q
www.ti.com
SNLS332E –JUNE 2010–REVISED APRIL 2013
DS90UB903Q Pin Diagram
Serializer - DS90UB903Q
40 Pin WQFN (Top View)
See Package Number RTA0040A
DS90UB903Q SERIALIZER PIN DESCRIPTIONS
Pin Name Pin No. I/O, Type Description
LVCMOS PARALLEL INTERFACE
DIN[20:0] 5, 4, 3, 2, 1, Inputs, Parallel data inputs.
40, 39, 38, 37, LVCMOS
36, 35, 33, 32, w/ pull down
30, 29, 28, 27,
26, 25, 24, 23
PCLK 6 Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
GENERAL PURPOSE OUTPUT (GPO)
GPO[3:0] 22, 21, 20, 19 Output, General-purpose output pins can be used to control and respond to various
LVCMOS commands.
BIDIRECTIONAL CONTROL BUS - I
2
C COMPATIBLE
Input/Output, Clock line for the bidirectional control bus communication
SCL 7
Open Drain SCL requires an external pull-up resistor to V
DDIO
.
Input/Output, Data line for the bidirectional control bus communication
SDA 8
Open Drain SDA requires an external pull-up resistor to V
DDIO
.
I
2
C Mode select
MODE = L, Master mode (default); Device generates and drives the SCL clock line.
Device is connected to slave peripheral on the bus. (Serializer initially starts up in
Input, LVCMOS
MODE 12 Standby mode and is enabled through remote wakeup by Deserializer)
w/ pull down
MODE = H, Slave mode; Device accepts SCL clock input and attached to an I
2
C
controller master on the bus. Slave mode does not generate the SCL clock, but uses
the clock generated by the Master for the data transfers.
Device ID Address Select
ID[x] 9 Input, analog
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3
CONTROL AND CONFIGURATION
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