Datasheet

DS90CR285, DS90CR286

SNLS130C –MARCH 1999–REVISED MARCH 2013

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Receiver Switching Characteristics (continued)

Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

RSPos0 Receiver Input Strobe Position for Bit 0

(2)

(Figure 21) f = 66 MHz 0.7 1.1 1.4 ns

RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns

RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns

RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns

RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns

RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns

RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns

RSKM RxIN Skew Margin

(3)

(Figure 22) f = 40 MHz 490 ps

f = 66 MHz 400 ps

RCOP RxCLK OUT Period (Figure 11) 15 T 50 ns

RCOH RxCLK OUT High Time (Figure 11) f = 40 MHz 6.0 10.0 ns

f = 66 MHz 4.0 6.1 ns

RCOL RxCLK OUT Low Time (Figure 11) f = 40 MHz 10.0 13.0 ns

f = 66 MHz 6.0 7.8 ns

RSRC RxOUT Setup to RxCLK OUT (Figure 11) f = 40 MHz 6.5 14.0 ns

f = 66 MHz 2.5 8.0 ns

RHRC RxOUT Hold to RxCLK OUT (Figure 11) f = 40 MHz 6.0 8.0 ns

f = 66 MHz 2.5 4.0 ns

RCCD RxCLK IN to RxCLK OUT Delay (Figure 13) f = 40 MHz 4.0 6.7 8.0 ns

f = 66 MHz 5.0 6.6 9.0 ns

RPLLS Receiver Phase Lock Loop Set (Figure 15) 10 ms

RPDD Receiver Powerdown Delay (Figure 19) 1 μs

(2) The min. and max. limits are based on the worst bit by applying a −400ps/+300ps shift from ideal position.

(3) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter

pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS

interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter less than 250 ps).

AC TIMING DIAGRAMS

Figure 5. “Worst Case” Test Pattern

Product Folder Links: DS90CR285 DS90CR286