Datasheet

DS90CR216A, DS90CR286A
www.ti.com SNLS043F –MAY 2000–REVISED FEBRUARY 2013
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
(1)
+ ISI (Inter-symbol interference)
(2)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
(1) Cycle-to-cycle jitter is less than TBD ps at 66 MHz.
(2) ISI is dependent on interconnect length; may be zero.
Figure 13. Receiver LVDS Input Skew Margin
DS90CR286A PIN DESCRIPTIONS — DGG0056A Package — 28-Bit Channel Link Receiver
Pin Name I/O No. Description
RxIN+ I 4 Positive LVDS differentiaI data inputs.
RxIN− I 4 Negative LVDS differential data inputs.
RxOUT O 28 TTL level data outputs.
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN− I 1 Negative LVDS differential clock input.
RxCLK OUT O 1 TTL Ievel clock output. The rising edge acts as data strobe.
PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low.
V
CC
I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL V
CC
I 1 Power supply for PLL.
PLL GND I 2 Ground pin for PLL.
LVDS V
CC
I 1 Power supply pin for LVDS inputs.
LVDS GND I 3 Ground pins for LVDS inputs.
DS90CR216A PIN DESCRIPTIONS — DGG0048A Package — 21-Bit Channel Link Receiver
Pin Name I/O No. Description
RxIN+ I 3 Positive LVDS differentiaI data inputs.
(1)
RxIN− I 3 Negative LVDS differential data inputs.
(1)
RxOUT O 21 TTL level data outputs.
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN− I 1 Negative LVDS differential clock input.
RxCLK OUT O 1 TTL Ievel clock output. The rising edge acts as data strobe.
PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low.
V
CC
I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL V
CC
I 1 Power supply for PLL.
(1) These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under
these conditions receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also
floating/terminated outputs will remain in the last valid state. A floating/terminated clock input will result in a LOW clock output.
Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DS90CR216A DS90CR286A