Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - customised TSSOP 56

Transmitter Switching Characteristics (Continued)

Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

TPLLS Transmitter Phase Lock Loop Set

(Figure 11 )

10 ms

TPDD Transmitter Power Down Delay

(Figure 15 )

100 ns

Receiver Switching Characteristics

Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

CLHT CMOS/TTL Low-to-High Transition Time

(Figure 4 )

2.2 5.0 ns

CHLT CMOS/TTL High-to-Low Transition Time

(Figure 4 )

2.2 5.0 ns

RSPos0 Receiver Input Strobe Position for Bit 0

(Figure 18 )

f = 65 MHz 0.7 1.1 1.4 ns

RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns

RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns

RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns

RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns

RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns

RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns

RSKM RxIN Skew Margin (Note 5)

(Figure 19 )

f = 65 MHz 400 ps

RCOP RxCLK OUT Period

(Figure 8)

15 T 50 ns

RCOH RxCLK OUT High Time

(Figure 8 )

f = 65 MHz 7.3 8.6 ns

RCOL RxCLK OUT Low Time

(Figure 8)

3.45 4.9 ns

RSRC RxOUT Setup to RxCLK OUT

(Figure 8 )

2.5 6.9 ns

RHRC RxOUT Hold to RxCLK OUT

(Figure 8 )

2.5 5.7 ns

RCCD RxCLK IN to RxCLK OUT Delay 25˚C, V

= 3.3V

(Figure 10 )

5.0 7.1 9.0 ns

RPLLS Receiver Phase Lock Loop Set

(Figure 12 )

10 ms

RPDD Receiver Power Down Delay

(Figure 16 )

1µs

Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min

and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows for LVDS interconnect skew, inter-symbol

interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).

AC Timing Diagrams

DS012887-3

FIGURE 1. “Worst Case” Test Pattern

DS90C383/DS90CF384