Datasheet

DS90C3202

SNLS191D –APRIL 2005–REVISED APRIL 2013

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Address R/W RESET Bit # Description Default Value

31d/1fh R/W None [7:6] 11; LVTTL Outputs available as long as "NO CLK" is at 0000_0000

HIGH regardless PLL lock or not

10; LVTTL Outputs available after 1K of CLK cycles

detected & PLL generated strobes are within 0.5UI respect

to REFCLK

01; LVTLL Outputs available after 2K of CLK cycles

detected

00: default ; LVTTL Outputs available after 1K of CLK cycles

detected

[5] 0: default; to select the size of wait counter between 1K or

2K, default is 1K

[4] I/O disable control for RXO channel A,

1: disable, 0: enable (default)

[3] I/O disable control for RXO channel B,

1 disable, 0: enable (default)

[2] I/O disable control for RXO channel C,

1: disable, 0: enable (default)

[1] I/O disable control for RXO channel D,

1: disable, 0: enable (default)

[0] I/O disable control for RXO channel E,

1: disable, 0: enable (default)

Product Folder Links: DS90C3202