Datasheet

RCLK OUT
RCOP
V
DD
/2
V
DD
/2
RFB=0
RFB=1
V
DD
/2 V
DD
/2
RCLK OUT
V
DD
/2
RCLK OUT
V
DD
/2
RCLK OUT
V
DD
/2
RSRC
RHRC
V
DD
/2
RSRC RHRC
V
DD
/2
V
DD
/2
Balanced RSRC / RHRC
Register addr 29d/1dh bit[2:1]=00b (default)
RSRC Increased by 1UI, RHRC Decreased by 1 UI
Register addr 29d/1dh bit[2:1]=01b
RSRC Decreased by 1UI, RHRC Increased by 1 UI
Register addr 29d/1dh bit[2:1]=10b
RSRC Increased by 2UI, RHRC Decreased by 2 UI
Register addr 29d/1dh bit[2:1]=11b
V
DD
/2 V
DD
/2
Additional +0.5 UI RSRC on
RXEA,C,E[6:0]; RXOB,D[6:0]
-0.5 UI Less RHRC on
RXEA,C,E[6:0]; RXOB,D[6:0]
RXEB,D[6:0]
RXOA,C,E[6:0]
RXEA,C,E[6:0]
RXOB,D[6:0]
RSRC
RHRC
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013 www.ti.com
AC Timing Diagrams (continued)
Figure 16. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Enabled
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