Datasheet

RCOH
RCOL
RCLK OUT
RCOP
V
DD
/2 V
DD
/2
RFB=0
RFB=1
RXOA,B,C,D,E[6:0]
V
DD
/2 V
DD
/2
RXEA,B,C,D,E[6:0]
RCLK OUT
V
DD
/2
RCLK OUT
V
DD
/2
RCLK OUT
V
DD
/2
RSRC
RHRC
-1 UI+1 UI
RSRC
RHRC
+1 UI-1 UI
V
DD
/2
RSRC
RHRC
-2 UI+2 UI
V
DD
/2
V
DD
/2
Balanced RSRC / RHRC
Register addr 29d/1dh bit[2:1]=00b (default)
RSRC Increased by 1UI, RHRC Decreased by 1UI
Register addr 29d/1dh bit[2:1]=01b
RSRC Decreased by 1UI, RHRC Increased by 1UI
Register addr 29d/1dh bit[2:1]=10b
RSRC Increased by 2UI, RHRC Decreased by 2UI
Register addr 29d/1dh bit[2:1]=11b
RXEB,D[6:0]
RCOH
RCOL
RCLK OUT
RCOP
V
DD
/2 V
DD
/2
V
DD
/2 V
DD
/2
RXOA,C,E[6:0]
RFB=0
RFB=1
RXEA,C,E[6:0]
V
DD
/2
RXOB,D[6:0]
1/2 UI1/2 UI
DS90C3202
www.ti.com SNLS191D –APRIL 2005–REVISED APRIL 2013
AC Timing Diagrams (continued)
RegisterAddress 29d/1dh bit [2:1] = 00b
Figure 14. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled
Figure 15. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Disabled
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: DS90C3202