Datasheet

Setup
V
DD
/2
Hold
t
DIH
t
DIS
TCLK
DIN [0:23]
t
TCP
0V
V
DD
/2
V
DD
/2 V
DD
/2V
DD
/2
V
DD
80%
20%
80%
20%
t
CLKT
t
CLKT
TCLK
V
DD
0V
80%
20%
80%
20%
Vdiff = 0V
t
LLHT
t
LHLT
Differential
Signal
Vdiff = (DOUT+) - (DOUT-)
100:
DOUT+
DOUT-
10 pF
10 pF
RCLK
ODD ROUT
EVEN ROUT
Signal PatternDevice Pin Name
DS90C124, DS90C241
SNLS209L –NOVEMBER 2005–REVISED APRIL 2013 www.ti.com
Figure 2. Deserializer Output Checkerboard Pattern
Figure 3. Serializer LVDS Output Load and Transition Times
Figure 4. Serializer Input Clock Transition Times
Figure 5. Serializer Setup/Hold Times
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