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DS80PCI800

www.ti.com

SNLS334E –APRIL 2011–REVISED MARCH 2012

DS80PCI800 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 8 Channel PCI Express

Repeater with Equalization and De-Emphasis

Check for Samples: DS80PCI800

FEATURES

mode)

• 0.2 UI of residual deterministic jitter at 8 Gbps

• Comprehensive family, proven system inter-

after 40” of FR4 or 10m 30awg PCIe Cable

operability

• Low power dissipation with ability to turnoff

– DS80PCI102 : x1 PCIe Gen-1/2/3

unused channels: 65 mW/channel

– DS80PCI402 : x4 PCIe Gen-1/2/3

• Automatic receiver detect (hot-plug)

– DS80PCI800 : x8/x16 PCIe Gen-1/2/3

• Multiple configuration modes:

• Automatic rate detect and adaptation to Gen-

Pins/SMbus/Direct-EEPROM load

1/2/3 speeds

• Flow-thru pinout: 54-pin LLP (10 mm x 5.5 mm,

• Seamless support for Gen-3 transmit FIR

0.5 mm pitch)

handshake

• Single supply voltage: 2.5V or 3.3V (selectable)

• Rate adaptive receive EQ (up to 36 dB),

• 3 kV HBM ESD rating

transmit de-emphasis (up to 12 dB) only Gen-

1/2

• −40 to 85°C operating temperature range

• Adjustable Transmit VOD: 0.8 to 1.3 Vp-p (pin

DESCRIPTION

The DS80PCI800 is a low power, 8 channel repeater with 4-stage input equalization, and output de-emphasis

driver to enhance the reach of PCI express serial links in board-to-board or cable interconnects. Ideal for higher

density x8 and x16 PCI express configurations, the DS80PCI800 automatically detects and adapts to Gen-1,

Gen-2 and Gen-3 data rates for easy system upgrade.

Each channel supports seamless detection and management of the new Gen-3 transmit equalizer coefficients

(FIR tap) handshake protocol and PCIe control signals such as transmit idle, beacon etc. without external system

intervention. An automatic receive detection circuitry controls the input termination impedance based upon

endpoint insertion (hot-plug events). These features guarantee PCIe interoperability at both the electrical and

system level, while reducing design complexity.

12 dB), transmit VOD (up to 1300 mVp-p) and receive equalization (up to 36 dB) to enable longer distance

transmission in lossy copper cables (10m+), or backplanes (40”+) with multiple connectors. The receiver is

capable of opening an input eye that is completely closed due to inter-symbol interference (ISI) introduced by the

interconnect medium.

The programmable settings can be applied easily via pins, software (SMBus/I2C) or loaded via an external

EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power

up, which eliminates the need for an external microprocessor or software driver.

With a low power consumption and control to turn-off unused channels, the DS80PCI800 is part of National's

PowerWise family of energy efficient devices.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (45 pages)

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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 DS80PCI800 2.5 Gbps / 5.0 Gbps / 8.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.
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DS80PCI800 www.ti.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Pin Descriptions (continued) Pin Name Pin Number I/O, Type Pin Description OUTB_0+, OUTB_1+, OUTB_2+, OUTB_3+, OUTB_0-, OUTB_1-, OUTB_2-, OUTB_3-, 45, 44, 43, 42, 40, 39, 38, 37 O Inverting and non-inverting 50Ω driver bank A outputs with de-emphasis. Compatible with AC coupled CML inputs.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Pin Descriptions (continued) Pin Name Pin Number I/O, Type Pin Description 27 O, LVCMOS Valid Register Load Status Output HIGH = External EEPROM load failed LOW = External EEPROM load passed VIN 24 Power In 3.3V mode, feed 3.3V to VIN In 2.5V mode, leave floating VDD 9, 14, 36, 41, 51 Power Power supply pins CML/analog 2.5V mode, connect to 2.5V supply 3.3V mode, connect 0.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Recommended Operating Conditions (continued) Ambient Temperature +85 °C SMBus (SDA, SCL) -40 3.6 V Supply Noise up to 50 MHz 100 mVp-p (1) (1) 6 25 Allowed supply noise (mVp-p sine wave) under typical conditions.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Electrical Characteristics Symbol Parameter Conditions Power Dissipation Min Typ Max Units VDD = 2.5 V supply, EQ Enabled, VOD = 1.0 Vp-p, RXDET = 1, PRSNT = 0 500 700 mW VIN = 3.3 V supply, EQ Enabled, VOD = 1.0 Vp-p, RXDET = 1, PRSNT = 0 660 900 mW Power PD LVCMOS / LVTTL DC Specifications Vih High Level Input Voltage 2.0 3.6 V Vil Low Level Input Voltage 0 0.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Electrical Characteristics (continued) Vtx-diff-pp Output Voltage Differential Swing Differential measurement with OUT_n+ and OUT_n-, terminated by 50Ω to GND, AC-Coupled, VID = 1.0 Vp-p, DEM0 = 1, DEM1 = 0, 0.8 1.0 1.2 Vp-p (1) Vtx-de-ratio_3.5 TX de-emphasis ratio VOD = 1.0 Vp-p, DEM0 = 0, DEM1 = R, GEN 1, 2 modes only -3.5 dB Vtx-de-ratio_6 TX de-emphasis ratio VOD = 1.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Electrical Characteristics (continued) DJE1 Residual deterministic jitter at 8 Gbps 35” 4mils FR4, VID = 0.8 Vp-p, PRBS15, EQ = 1F'h, DEM = 0 dB 0.14 UI DJE2 Residual deterministic jitter at 5 Gbps 35” 4mils FR4, VID = 0.8 Vp-p, PRBS15,EQ = 1F'h, DEM = 0 dB 0.1 UI DJE3 Residual deterministic jitter at 2.5 Gbps 35” 4mils FR4, VID = 0.8 Vp-p, PRBS15, EQ = 1F'h, DEM = 0 dB 0.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Electrical Characteristics — Serial Management Bus Interface Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ Max Units 0.8 V 3.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 + IN 0V tPHLD tPLHD + OUT 0V - Figure 3. Propagation Delay Timing Diagram + IN 0V DATA tDATA-IDLE tIDLE-DATA + OUT 0V DATA IDLE IDLE Figure 4. Transmit IDLE-DATA and DATA-IDLE Response Time tLOW tR tHIGH SCL tHD:STA tBUF tHD:DAT tF tSU:STA tSU:DAT tSU:STO SDA SP ST ST SP Figure 5.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected via pin for each side independently. When de-emphasis is asserted VOD is automatically adjusted per the De- Emphasis table below. The RXDET pins provides automatic and manual control for input termination (50Ω or >50KΩ). RATE setting is also pin controllable with pin selections (Gen 1/2, auto detect and Gen 3).
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 3.3V mode 2.5V mode VDD_SEL Enable VDD_SEL open VIN open Disable 3.3V 10 uF 1 uF VIN Internal voltage regulator 2.5V VDD VDD 0.1 uF 0.1 uF VDD VDD 0.1 uF 0.1 uF 1 uF 2.5V Capacitors can be either tantalum or an ultra-low ESR seramic. 10 uF Internal voltage regulator Capacitors can be either tantalum or an ultra-low ESR seramic. VDD VDD 0.1 uF 0.1 uF VDD VDD 0.1 uF 0.1 uF VDD VDD 0.1 uF 0.1 uF Place 0.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Table 2. Equalizer Settings (continued) 2 0 R 0000 0001 = 0x01 3.4 5.8 7.9 FR4 5 inch 5–mil trace 3 0 Float 0000 0010 = 0x02 4.8 7.7 9.9 FR4 5 inch 4–mil trace 4 0 1 0000 0011 = 0x03 5.9 8.9 11.0 FR4 10 inch 5–mil trace 5 R 0 0000 0111 = 0x07 7.2 11.2 14.3 FR4 10 inch 4–mil trace 6 R R 0001 0101 = 0x15 6.1 11.4 14.6 FR4 15 inch 4–mil trace 7 R Float 0000 1011 = 0x0B 8.8 13.5 17.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Table 4.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Table 6.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Table 6.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Table 6.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Table 7.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Table 7. Example of EEPROM for 4 Devices using 2 Address Maps (continued) 47 2F 0x54 End Device 0, 1 - Address Offset 39 48 30 0x00 Begin Device 2, 3 - Address Offset 3 49 31 0x00 50 32 0x04 51 33 0x07 52 34 0x00 53 35 0x00 EQ CHB0 = 00 54 36 0xAB VOD CHB0 = 1.0V 55 37 0x00 DEM CHB0 = 0 (0dB) 56 38 0x00 EQ CHB1 = 00 57 39 0x0A VOD CHB1 = 1.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Table 8. Device Slave Address Bytes AD[3:0] Settings Address Bytes (HEX) 0000 B0 0001 B2 0010 B4 0011 B6 0100 B8 0101 BA 0110 BC 0111 BE 1000 C0 1001 C2 1010 C4 1011 C6 1100 C8 1101 CA 1110 CC 1111 CE The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant. External pull-up resistor is required on the SDA. The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 2. The Device (Slave) drives the ACK bit (“0”). 3. The Host drives the 8-bit Register Address. 4. The Device drives an ACK bit (“0”). 5. The Host drives a START condition. 6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ. 7. The Device drives an ACK bit “0”. 8. The Device drives the 8-bit data value (register contents). 9.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x08 Override Pin Control 7 Reserved R/W 0x00 Set bit to 0. 6 Override SD_TH 1: Block SD_TH pin control 0: Allow SD_TH pin control 5 Reserved Set bit to 0.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x11 CH0 - CHB0 DEM 7 RXDET STATUS R 0x02 Observation bit for RXDET CH0 - CHB0. 1: RX = detected 0: RX = not detected 6:5 RATE_DET STATUS R Observation bit for RATE_DET CH0 - CHB0. 00: GEN1 (2.5G) 01: GEN2 (5G) 11: GEN3 (8G) 4:3 Reserved R/W Set bits to 0.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x17 CH1 - CHB1 VOD 7 Short Circuit Protection R/W 0xAD 1: Enable the short circuit protection 0: Disable the short circuit protection 6 RATE_SEL 1: Gen 1/2, 0: Gen 3 Note: override the RATE pin. 5:3 Reserved Set bits to default value - 101. 2:0 VOD Control OB1 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x1C CH2 - CHB2 IDLE, RXDET 7:6 Reserved R/W 0x00 Set bits to 0. 5 IDLE_AUTO 1: Automatic IDLE detect 0: Allow IDLE_SEL control in bit 4 Note: override IDLE control. 4 IDLE_SEL 1: Output is MUTED (electrical idle) 0: Output is ON Note: override IDLE control.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x20 CH2 - CHB2 IDLE Threshold 7:4 Reserved R/W 0x00 Set bits to 0. 3:2 IDLE thd De-assert threshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note: override the SD_TH pin.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x26 CH3 - CHB3 DEM 7 RXDET STATUS R 0x02 Observation bit for RXDET CH3 - CHB3. 1: RX = detected 0: RX = not detected 6:5 RATE_DET STATUS R Observation bit for RATE_DET CH3 - CHB3. 00: GEN1 (2.5G) 01: GEN2 (5G) 11: GEN3 (8G) 4:3 Reserved R/W Set bits to 0.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x2D CH4 - CHA0 VOD 7 Short Circuit Protection R/W 0xAD 1: Enable the short circuit protection 0: Disable the short circuit protection 6 RATE_SEL 1: Gen 1/2, 0: Gen 3 Note: override the RATE pin. 5:3 Reserved Set bits to default value - 101. 2:0 VOD Control OA0 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x32 CH5 - CHA1 IDLE, RXDET 7:6 Reserved R/W 0x00 Set bits to 0. 5 IDLE_AUTO 1: Automatic IDLE detect 0: Allow IDLE_SEL control in bit 4 Note: override IDLE control. 4 IDLE_SEL 1: Output is MUTED (electrical idle) 0: Output is ON Note: override IDLE control.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x36 CH5 - CHA1 IDLE Threshold 7:4 Reserved R/W 0x00 Set bits to 0. 3:2 IDLE thd De-assert threshold 00 = 110 mVp-p (default) 01 = 100 mVp-p 10 = 150 mVp-p 11 = 130 mVp-p Note: override the SD_TH pin.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x3C CH6 - CHA2 DEM 7 RXDET STATUS R 0x02 Observation bit for RXDET CH6 - CHA2. 1: RX = detected 0: RX = not detected 6:5 RATE_DET STATUS R Observation bit for RATE_DET CH6 - CHA2. 00: GEN1 (2.5G) 01: GEN2 (5G) 11: GEN3 (8G) 4:3 Reserved R/W Set bits to 0.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Table 9. SMBUS Slave Mode Register Map (continued) Address Register Name Bit (s) Field Type Default Description 0x42 CH7 - CHA3 VOD 7 Short Circuit Protection R/W 0xAD 1: Enable the short circuit protection 0: Disable the short circuit protection 6 RATE_SEL 1: Gen 1/2, 0: Gen 3 Note: override the RATE pin. 5:3 Reserved Set bits to default value - 101. 2:0 VOD Control OA3 VOD Control 000: 0.7 V 001: 0.8 V 010: 0.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential impedance of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias should be avoided if possible.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com POWER SUPPLY BYPASSING Two approaches are recommended to ensure that the DS80PCI800 is provided with an adequate power supply. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance.
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DS80PCI800 www.ti.com SNLS334E – APRIL 2011 – REVISED MARCH 2012 1020 VDD = 2.5 V VOD (mVp-p) 1018 1016 1014 1012 - 40 -15 10 35 60 85 TEMPERATURE (°C) Figure 10. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Temperature Typical Performance Eye Diagrams Characteristics Pattern Generator VID = 1.0 Vp-p, DE = 0 dB 8 Gb/s, PRBS23 TL Lossy Channel IN DS80PCI800 Scope BW = 50 GHz OUT Figure 11. Test Setup Connections Diagram Figure 12.
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DS80PCI800 SNLS334E – APRIL 2011 – REVISED MARCH 2012 www.ti.com Figure 13. TL = 35 inch 4–mil FR4 trace, DS80PCI800 settings: EQ[1:0] = float, R = 1F'h, DEM[1:0] = float, float Pattern Generator VID = 1.0 Vp-p, DE = -9 dB 8 Gb/s, PRBS23 TL1 Lossy Channel IN DS80PCI800 OUT TL2 Lossy Channel Scope BW = 50 GHz Figure 14. Test Setup Connections Diagram Figure 15.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS80PCI800SQ/NOPB WQFN NJY 54 2000 330.0 16.4 5.8 10.3 1.0 12.0 16.0 Q1 DS80PCI800SQE/NOPB WQFN NJY 54 250 178.0 16.4 5.8 10.3 1.0 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS80PCI800SQ/NOPB WQFN NJY 54 2000 367.0 367.0 38.0 DS80PCI800SQE/NOPB WQFN NJY 54 250 213.0 191.0 55.
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PACKAGE OUTLINE NJY0054A WQFN SCALE 2.000 WQFN 5.6 5.4 B A PIN 1 INDEX AREA 0.5 0.3 0.3 0.2 10.1 9.9 DETAIL OPTIONAL TERMINAL TYPICAL 0.8 MAX C SEATING PLANE 2X 4 SEE TERMINAL DETAIL 3.51±0.1 19 (0.1) 27 28 18 50X 0.5 7.5±0.1 2X 8.5 1 45 54 PIN 1 ID (OPTIONAL) 46 54X 54X 0.5 0.3 0.3 0.2 0.1 0.05 C A C B 4214993/A 07/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2.
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EXAMPLE BOARD LAYOUT NJY0054A WQFN WQFN (3.51) SYMM 54X (0.6) 54 54X (0.25) SEE DETAILS 46 1 45 50X (0.5) (7.5) SYMM (9.8) (1.17) TYP 2X (1.16) 28 18 ( 0.2) TYP VIA 19 27 (1) TYP (5.3) LAND PATTERN EXAMPLE SCALE:8X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL SOLDER MASK DEFINED SOLDER MASK DETAILS 4214993/A 07/2013 NOTES: (continued) 4.
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EXAMPLE STENCIL DESIGN NJY0054A WQFN WQFN SYMM METAL TYP (0.855) TYP 46 54 54X (0.6) 54X (0.25) 1 45 50X (0.5) (1.17) TYP SYMM (9.8) 12X (0.97) 18 28 19 27 12X (1.51) (5.3) SOLDERPASTE EXAMPLE BASED ON 0.125mm THICK STENCIL EXPOSED PAD 67% PRINTED SOLDER COVERAGE BY AREA SCALE:10X 4214993/A 07/2013 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.
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