Datasheet

DS64BR401
SNLS304G –JUNE 2009–REVISED APRIL 2013 www.ti.com
Table 1. PIN DESCRIPTIONS
Pin Name Pin Number I/O, Type Pin Descriptions
Differential High Speed I/O's
IA_0+, IA_0- , 10, 11 I, CML Inverting and non-inverting CML differential inputs to the equalizer. A
IA_1+, IA_1-, 12, 13 gated on-chip 50Ω termination resistor connects INA_n+ to VDD and
IA_2+, IA_2-, 15, 16 INA_n- to VDD when enabled.
IA_3+, IA_3- 17, 18
OA_0+, OA_0-, 35, 34 O, LPDS Inverting and non-inverting low power differential signaling (LPDS) 50Ω
OA_1+, OA_1-, 33, 32 outputs with de-emphasis. Compatible with AC coupled CML inputs.
OA_2+, OA_2-, 31, 30
OA_3+, OA_3- 29, 28
IB_0+, IB_0- , 45, 44 I, CML Inverting and non-inverting CML differential inputs to the equalizer. A
IB_1+, IB_1-, 43, 42 gated on-chip 50Ω termination resistor connects INB_n+ to VDD and
IB_2+, IB_2-, 40, 39 INB_n- to VDD when enabled.
IB_3+, IB_3- 38, 37
OB_0+, OB_0-, 1, 2 O, LPDS Inverting and non-inverting low power differential signaling (LPDS) 50Ω
OB_1+, OB_1-, 3, 4 outputs with de-emphasis. Compatible with AC coupled CML inputs.
OB_2+, OB_2-, 5, 6
OB_3+, OB_3- 7, 8
Control Pins — Shared (LVCMOS)
ENSMB 48 I, LVCMOS w/ System Management Bus (SMBus) enable pin.
internal pull- When pulled high provide access internal digital registers that are a
down means of auxiliary control for such functions as equalization, de-
emphasis, VOD, rate, and idle detection threshold.
When pulled low, access to the SMBus registers are disabled and
SMBus function pins are used to control the Equalizer and De-Emphasis.
Please refer to SYSTEM MANAGEMENT BUS (SMBUS) AND
CONFIGURATION REGISTERS section and ELECTRICAL
CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE for
detail information.
ENSMB = 1 (SMBUS MODE)
SCL 50 I, LVCMOS ENSMB = 1
SMBUS clock input pin is enabled. External pull-up resistor maybe
needed. Refer to R
TERM
in the SMBus specification.
SDA 49 I, LVCMOS ENSMB = 1
O, Open Drain The SMBus bi-directional SDA pin is enabled. Data input or open drain
output. External pull-up resistor is required.
Refer to R
TERM
in the SMBus specification.
AD0–AD3 54, 53, 47, 46 I, LVCMOS w/ ENSMB = 1
internal pull- SMBus Slave Address Inputs. In SMBus mode, these pins are the user
down set SMBus slave address inputs. See section — SYSTEM
MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS
for additional information.
ENSMB = 0 (NORMAL PIN MODE)
EQA0, EQA1 20, 19 I, Float, EQA/B, 3–level controls the level of equalization of the A/B sides. The
EQB0, EQB1 46, 47 LVCMOS EQA/B pins are active only when ENSMB is de-asserted (Low). Each of
the 4 A/B channels have the same level unless controlled by the SMBus
control registers. When ENSMB goes high the SMBus registers provide
independent control of each lane. See Table 2,Table 3,Table 4
DEMA0, DEMA1 49, 50 I, Float, DEMA/B, 3–level controls the level of de-emphasis of the A/B sides. The
DEMB0, DEMB1 53, 54 LVCMOS DEMA/B pins are only active when ENSMB is de-asserted (Low). Each
of the 4 A/B channels have the same level unless controlled by the
SMBus control registers. When ENSMB goes High the SMBus registers
provide independent control of each lane. See Table 5
Control Pins — Both Modes (LVCMOS)
RATE 21 I, Float, RATE, 3–level controls the pulse width of de-emphasis of the output.
LVCMOS RATE = 0 forces 3 Gbps,
RATE = 1 forces 6 Gbps,
RATE = Float enables auto rate detection and the pulse width (pull-back)
is set appropriately after each exit from IDLE. This requires the transition
from IDLE to ACTIVE state — OOB signal. See Table 5
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