Datasheet

High Speed Serial CML Input
A0 B0
C0 D0
E0 A1 B1
C1 D1
E1 A2 B2
C2 D2
E2 A3 B3
C3 D3
E3
First Bit In
Last Bit In
Current CyclePrevious Cycle Next Cycle
Output Receive Clock
A0 A1 A2 A3
B0 B1 B2 B3
C0 C1 C2 C3
D0 D1 D2 D3
E0 E1 E2 E3
LVDS Data-0
LVDS Data-1
LVDS Data-2
LVDS Data-3
LVDS Data-4
DS32EL0124, DS32ELX0124
www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013
Figure 8. CML to LVDS Bit Map
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