Datasheet

SCL
SDA
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
1/f
scl
t
scl
t
sch
t
icf
t
icf
t
icr
t
sdh
t
sds
t
icr
t
vd
t
sth
Start Condition
1 2 3 4
SCL
SDA
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
9
D7/A
t
vd
t
sds
t
sps
t
buf
Stop Condition
Start Condition
8
DRV8830
SLVSAB2F –MAY 2010– REVISED FEBRUARY 2012 www.ti.com
I
2
C TIMING REQUIREMENTS
(1)
V
CC
= 2.75 V to 6.8 V, T
A
= -40°C to 85°C (unless otherwise noted)
STANDARD MODE FAST MODE UNIT
MIN TYP MAX MIN TYP MAX
f
scl
I
2
C clock frequency 0 100 0 400 kHz
t
sch
I
2
C clock high time 4 0.6 µs
t
scl
I
2
C clock low time 4.7 1.3 µs
t
sp
I
2
C spike time 0 50 0 50 ns
t
sds
I
2
C serial data setup time 250 100 ns
t
sdh
I
2
C serial data hold time 0 0 ns
t
icr
I
2
C input rise time 1000 20+0.1Cb
(2)
300 ns
t
icf
I
2
C input fall time 300 20+0.1Cb
(2)
300 ns
t
ocf
I
2
C output fall time 300 20+0.1Cb
(2)
300 ns
t
buf
I
2
C bus free time 4.7 1.3 µs
t
sts
I
2
C Start setup time 4.7 0.6 µs
t
sth
I
2
C Start hold time 4 0.6 µs
t
sps
I
2
C Stop setup time 4 0.6 µs
t
vd
(data) Valid data time (SCL low to SDA valid) 1 1 µs
Valid data time of ACK (ACK signal from SCL low
t
vd
(ack) 1 1 µs
to SDA low)
(1) Not production tested.
(2) C
b
= total capacitance of one bus line in pF
Figure 1. I
2
C Timing Requirements
Figure 2. I
2
C Timing Requirements
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