Datasheet

DRV8412
DRV8432
SLES242C –DECEMBER 2009–REVISED MAY 2010 www.ti.com
THEORY OF OPERATION
Special attention should be paid to the power-stage
POWER SUPPLIES
power supply; this includes component selection,
PCB placement, and routing. As indicated, each
To facilitate system design, the DRV8412/32 need
half-bridge has independent power-stage supply pin
only a 12-V supply in addition to H-Bridge power
(PVDD_X). For optimal electrical performance, EMI
supply (PVDD). An internal voltage regulator provides
compliance, and system reliability, it is important that
suitable voltage levels for the digital and low-voltage
each PVDD_X pin is decoupled with a ceramic
analog circuitry. Additionally, the high-side gate drive
capacitor (X5R or better) placed as close as possible
requiring a floating voltage supply, which is
to each supply pin. It is recommended to follow the
accommodated by built-in bootstrap circuitry requiring
PCB layout of the DRV8412/32 EVM board.
external bootstrap capacitor.
The 12-V supply should be from a low-noise,
To provide symmetrical electrical characteristics, the
low-output-impedance voltage regulator. Likewise, the
PWM signal path, including gate drive and output
50-V power-stage supply is assumed to have low
stage, is designed as identical, independent
output impedance and low noise. The power-supply
half-bridges. For this reason, each half-bridge has a
sequence is not critical as facilitated by the internal
separate gate drive supply (GVDD_X), a bootstrap
power-on-reset circuit. Moreover, the DRV8412/32
pin (BST_X), and a power-stage supply pin
are fully protected against erroneous power-stage
(PVDD_X). Furthermore, an additional pin (VDD) is
turn-on due to parasitic gate charging. Thus,
provided as supply for all common circuits. Special
voltage-supply ramp rates (dv/dt) are non-critical
attention should be paid to place all decoupling
within the specified voltage range (see the
capacitors as close to their associated pins as
Recommended Operating Conditions section of this
possible. In general, inductance between the power
data sheet).
supply pins and decoupling capacitors must be
avoided. Furthermore, decoupling capacitors need a
short ground path back to the device. SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
For a properly functioning bootstrap circuit, a small
ceramic capacitor (an X5R or better) must be
Powering Up
connected from each bootstrap pin (BST_X) to the
power-stage output pin (OUT_X). When the The DRV8412/32 do not require a power-up
power-stage output is low, the bootstrap capacitor is sequence. The outputs of the H-bridges remain in a
charged through an internal diode connected high impedance state until the gate-drive supply
between the gate-drive power-supply pin (GVDD_X) voltage GVDD_X and VDD voltage are above the
and the bootstrap pin. When the power-stage output undervoltage protection (UVP) voltage threshold (see
is high, the bootstrap capacitor potential is shifted the Electrical Characteristics section of this data
above the output potential and thus provides a sheet). Although not specifically required, holding
suitable voltage supply for the high-side gate driver. RESET_AB and RESET_CD in a low state while
In an application with PWM switching frequencies in powering up the device is recommended. This allows
the range from 10 kHz to 500 kHz, the use of 100-nF an internal circuit to charge the external bootstrap
ceramic capacitors (X5R or better), size 0603 or capacitors by enabling a weak pulldown of the
0805, is recommended for the bootstrap supply. half-bridge output.
These 100-nF capacitors ensure sufficient energy
storage, even during minimal PWM duty cycles, to Powering Down
keep the high-side power stage FET fully turned on
The DRV8412/32 do not require a power-down
during the remaining part of the PWM cycle. In an
sequence. The device remains fully operational as
application running at a switching frequency lower
long as the gate-drive supply (GVDD_X) voltage and
than 10 kHz, the bootstrap capacitor might need to be
VDD voltage are above the UVP voltage threshold
increased in value.
(see the Electrical Characteristics section of this data
sheet). Although not specifically required, it is a good
practice to hold RESET_AB and RESET_CD low
during power down to prevent any unknown state
during this transition.
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