Datasheet

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GVDD

PVDD

Controller

RESET_AB

PWM_B

OC_ADJ

GND

GND_A

GND_B

OUT_B

PVDD_B

AGND

VREG

BST_B

BST_C

PVDD_C

OUT_C

RESET_CD

PWM_D

VDD

GVDD_C

OUT_D

PVDD_D

BST_D

GVDD_D

PWM_C

GND_D

GND_C

GVDD_B

OTW

FAULT

PWM_A

GVDD_A

BST_A

PVDD_A

OUT_A

DRV8412

DRV8432

www.ti.com

SLES242C –DECEMBER 2009–REVISED MAY 2010

Dual Full Bridge PWM Motor Driver

Check for Samples: DRV8412, DRV8432

The DRV8412/32 require two power supplies, one at

FEATURES

12 V for GVDD and VDD, and another up to 50 V for

• High-Efficiency Power Stage (up to 97%) with

PVDD. The DRV8412/32 can operate at up to

Low R

DS(on)

MOSFETs (80 mΩ at T

= 25°C)

500-kHz switching frequency while still maintain

• Operating Supply Voltage up to 50 V

precise control and high efficiency. They also have an

(70 V Absolute Maximum)

innovative protection system safeguarding the device

against a wide range of fault conditions that could

• DRV8412 (power pad down): up to 2 x 3 A

damage the system. These safeguards are

Continuous Output Current (2 x 6 A Peak) in

short-circuit protection, overcurrent protection,

Dual Full Bridge Mode or 6 A Continuous

undervoltage protection, and two-stage thermal

Current in Parallel Mode (12 A Peak)

protection. The DRV8412/32 have a current-limiting

• DRV8432 (power pad up): up to 2 x 7 A

circuit that prevents device shutdown during load

Continuous Output Current ( 2 x 12 A Peak) in

transients such as motor start-up. A programmable

Dual Full Bridge Mode or 14 A Continuous

overcurrent detector allows adjustable current limit

and protection level to meet different motor

Current in Parallel Mode (24 A Peak)

requirements.

• PWM Operating Frequency up to 500 kHz

The DRV8412/32 have unique independent supply

• Integrated Self-Protection Circuits Including

and ground pins for each half bridge, which makes it

Undervoltage, Overtemperature, Overload, and

possible to provide current measurement through

Short Circuit

external shunt resistor and support multiple motors

• Programmable Cycle-by-Cycle Current Limit

with different power supply voltage requirements.

Protection

Simplified Application Diagram

• Independent Supply and Ground Pins for Each

Half Bridge

• Intelligent Gate Drive and Cross Conduction

Prevention

• No External Snubber or Schottky Diode is

Required

APPLICATIONS

• Brushed DC and Stepper Motors

• Three Phase Permanent Magnet Synchronous

Motors

• Robotic and Haptic Control System

• Actuators and Pumps

• Precision Instruments

• TEC Drivers

DESCRIPTION

The DRV8412/32 are high performance, integrated

dual full bridge motor drivers with an advanced

protection system.

Because of the low R

DS(on)

of the H-Bridge MOSFETs

and intelligent gate drive design, the efficiency of

these motor drivers can be up to 97%, which enables

the use of smaller power supplies and heatsinks, and

are good candidates for energy efficient applications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
DRV8412 DRV8432 www.ti.
PAGE 2
DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 PACKAGE HEAT DISSIPATION RATINGS DRV8412 DRV8432 RqJC, junction-to-case (power pad / heat slug) thermal resistance PARAMETER 1.1 °C/W 0.9 °C/W RqJA, junction-to-ambient thermal resistance 25 °C/W This device is not intended to be used without a heatsink. Therefore, RqJA is not specified. See the Thermal Information section.
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DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com DEVICE INFORMATION Pin Assignment Here are the pinouts for the DRV8412/32: • DRV8412: 44-pin TSSOP power pad down DDW package. This package contains a thermal pad that is located on the bottom side of the device for dissipating heat through PCB. • DRV8432: 36-pin PSOP3 DKD package. This package contains a thick heat slug that is located on the top side of the device for dissipating heat through heatsink.
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DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 PIN NAME FUNCTION DESCRIPTION (1) DRV8412 DRV8432 M2 9 12 I Mode selection pin M3 10 11 I Reserved mode selection pin, AGND connection is recommended NC 3,4,19,20,25,42 – – No connection pin. Ground connection is recommended OC_ADJ 14 7 O Analog overcurrent programming pin, requires resistor to AGND OTW 21 2 O Overtemperature warning signal, open-drain, active-low. An internal pull-up resistor to VREG (3.
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DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com SYSTEM BLOCK DIAGRAM VDD 4 Undervoltage Protection OTW Internal Pullup Resistors to VREG FAULT M1 Protection and I/O Logic M2 M3 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD Isense OC_ADJ GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D FB/PFB−Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv. Ctrl.
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DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 ELECTRICAL CHARACTERISTICS TA = 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, fSw = 400 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.95 3.3 3.65 9 12 mA 2.
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DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS EFFICIENCY vs SWITCHING FREQUENCY (DRV8432) NORMALIZED RDS(on) vs GATE DRIVE 1.10 100 TJ = 25°C Normalized RDS(on) / (RDS(on) at 12 V) 90 80 Efficiency – % 70 60 50 40 30 Full Bridge 20 Load = 5 A PVDD = 50 V TC = 75°C 10 0 0 50 1.08 1.06 1.04 1.02 1.00 0.98 0.96 8.0 100 150 200 250 300 350 400 450 500 8.5 9.0 10.5 11.0 11.5 Figure 2.
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DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 TYPICAL CHARACTERISTICS (continued) OUTPUT DUTY CYCLE vs INPUT DUTY CYCLE 100 fS = 500 kHz TC = 25°C 90 Output Duty Cycle – % 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 Input Duty Cycle – % Figure 5.
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DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the DRV8412/32 need only a 12-V supply in addition to H-Bridge power supply (PVDD). An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, the high-side gate drive requiring a floating voltage supply, which is accommodated by built-in bootstrap circuitry requiring external bootstrap capacitor.
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DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 ERROR REPORTING Bootstrap Capacitor Under Voltage Protection The FAULT and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. When the device runs at a low switching frequency (e.g.
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DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com Figure 6 illustrates cycle-by-cycle operation with high side OC event and Figure 7 shows cycle-by-cycle operation with low side OC. Dashed lines are the operation waveforms when no CBC event is triggered and solide lines show the waveforms when CBC event is triggered.
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DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 DIFFERENT OPERATIONAL MODES The DRV8412/32 support four different modes of operation: 1. Dual full bridges (FB) (two PWM inputs each full bridge) or four half bridges (HB) with CBC current limit 2. Dual full bridges (two PWM inputs each full bridge) or four half bridges with OC latching shutdown (no CBC current limit) 3. Parallel full bridge (PFB) with CBC current limit 4.
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DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com During T_OC Period CBC with Low Side OC PVDD Current Limit Load Current PWM_HS PWM_HS Load PWM_LS PWM_LS T_LS T_OC T_HS GND_X Figure 7. Cycle-by-Cycle Operation with Low Side OC (dashed line: normal operation; solid line: CBC event) GVDD 1uF 330 uF PVDD 3.
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DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 GVDD 1uF PVDD 330 uF 3.
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DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com GVDD 1uF PVDD 330 uF 3.
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DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 GVDD 1uF PVDD 330 uF 3.3 1000 uF GVDD_B 1uF OTW GVDD_A 10 nF BST_A 100 nF PWM_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B 100nF Roc_adj TEC Controller 100nF 4.7 uH 4.7 uH 1 GND 47 uF PVDD_B AGND BST_B VREG BST_C 100 nF 100 nF 100 nF M3 47 uF PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D PWM_D 47 uF TEC FAULT PVDD_A 100nF 100nF 4.7 uH 47 uF 4.
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DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com APPLICATION INFORMATION SYSTEM DESIGN RECOMMENDATIONS Voltage of Decoupling Capacitor The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature, ripple current, and voltage overshoot must be considered. The high frequency decoupling capacitor should use ceramic capacitor with X5R or better rating. For a 50-V application, a minimum voltage rating of 63 V is recommended.
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DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 Because an inductor usually saturates pretty quickly after reaching its current rating, it is recommended to use an inductor with a doubled value or an inductor with a current rating well above the operating condition. Parallel Mode Operation For a device operated in parallel mode, a minimum of 30 nH to 100 nH inductance or a ferrite bead is required after the output pins (e.g.
PAGE 20
DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com GVDD C14 1.0ufd/16V 0603 U1 GND 44 1 43 C13 42 1.0ufd/16V 0603 41 PVDD 40 GND 2 + 3 C11 C12 47ufd/16V FC 0.1ufd/16V 0603 C15 C16 0.1ufd/100V 0805 0.1ufd/100V 0805 4 GND L1 39 GND 4.7uH/8.7A 931AS GND 38 5 OUTD Orange 37 6 GVDD 1 2 GRAY 6A/250V L2 GND J2 36 + C4 C5 330ufd/16V M 0.1ufd/16V 0603 4.7uH/8.7A 931AS 35 7 PVDD 8 GVDD = 12V 9 GND C18 C19 0.1ufd/100V 0805 0.
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DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 T1: PVDD decoupling capacitors C16, C19, C21, and C24 should be placed very close to PVDD_X pins and ground return path. T2: VREG decoupling capacitor C10 should be placed very close to VREG abd AGND pins. T3: Clear the space above and below the device as much as possible to improve the thermal spreading. T4: Add many vias to reduce the impedance of ground path through top to bottom side.
PAGE 22
DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com B1: Do not block the heat transfer path at bottom side. Clear as much space as possible for better heat spreading. Figure 16. Printed Circuit Board – Bottom Layer THERMAL INFORMATION The thermally enhanced package provided with the DRV8432 is designed to interface directly to heat sink using a thermal interface compound, (e.g., Ceramique from Arctic Silver, TIMTronics 413, etc.).
PAGE 23
DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 The thermal grease thermal resistance can be calculated from the exposed power pad or heat slug area and the thermal grease manufacturer's area thermal resistance (expressed in °C-in 2/W or °C-mm2/W). The approximate exposed heat slug size is as follows: • DRV8432, 36-pin PSOP3 …… 0.124 in2 (80 mm 2) The thermal resistance of thermal pads is considered higher than a thin thermal grease layer and is not recommended.
PAGE 24
DRV8412 DRV8432 SLES242C – DECEMBER 2009 – REVISED MAY 2010 www.ti.com REVISION HISTORY Changes from Revision A (December 2009) to Revision B Page • Added note to recommended operating conditions table ..................................................................................................... 2 • Added TA = 125°C power rating of 1.0 W to package power deratings table ......................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DRV8412DDWR HTSSOP DDW 44 2000 330.0 24.4 DRV8432DKDR HSSOP DKD 36 500 330.0 24.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.6 1.8 12.0 24.0 Q1 14.7 16.4 4.0 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8412DDWR HTSSOP DDW 44 2000 346.0 346.0 41.0 DRV8432DKDR HSSOP DKD 36 500 346.0 346.0 41.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.