Datasheet

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DP83848M
1.0 Pin Descriptions
The DP83848M pins are classified into the following inter-
face categories (each interface is described in the sec-
tions that follow):
— Serial Management Interface
— MAC Data Interface
— Clock Interface
— LED Interface
— Reset
— Strap Options
— 10/100 Mb/s PMD Interface
— Special Connect Pins
— Power and Ground pins
Note: Strapping pin option. Please see Section 1.61.6 for
strap definitions.
All DP83848M signal pins are I/O cells regardless of the
particular use. The definitions below define the functional-
ity of the I/O cells for each pin.
1.1 Serial Management Interface
1.2 MAC Data Interface
Type: I Input
Type: O Output
Type: I/O Input/Output
Type: PD,PU Internal Pulldown/Pullup
Type: S Strapping Pin (All strap pins have weak in-
ternal pull-ups or pull-downs. If the default
strap value is needed to be changed then an
external 2.2 kΩ resistor should be used.
Please see Section 1.6 1.6 for details.)
Signal Name Type Pin # Description
MDC I 25 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
management data input/output serial interface which may be
asynchronous to transmit and receive clocks. The maximum clock
rate is 25 MHz with no minimum clock rate.
MDIO I/O 24 MANAGEMENT DATA I/O: Bi-directional management instruc-
tion/data signal that may be sourced by the station management
entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.
Signal Name Type Pin # Description
TX_CLK O 2 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100
Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz
reference clock.
Unused in RMII mode. The device uses the X1 reference clock in-
put as the 50 MHz reference for both transmit and receive.
TX_EN I, PD 3 MII TRANSMIT ENABLE: Active high input indicates the pres-
ence of valid data inputs on TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the pres-
ence of valid data on TXD[1:0].
TXD_0
TXD_1
TXD_2
TXD_3
I
I, PD
4
5
6
7
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0],
that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s
mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0],
that accept data synchronous to the 50 MHz reference clock.
RX_CLK O 31 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive
clock for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock in-
put as the 50 MHz reference for both transmit and receive.
RX_DV O, PD 32 MII RECEIVE DATA VALID: Asserted high to indicate that valid
data is present on the corresponding RXD[3:0].
RMII Synchronous Receive Data Valid: This signal provides the
RMII Receive Data Valid indication independent of Carrier Sense.