Datasheet

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1
2
3
13
12
14
DCP02xU
28
27
26
C
16
R
7
C
17
C
18
R
8
C
20
C
19
VS4
0S4
+V4
COM4
-V4
NC
NC
1
2
3
13
12
14
C
11
R
5
C
13
C
12
R
6
C
14
C
15
VS3
0S3
+V3
COM3
-V3
28
27
26
C
1
R
1
C
3
C
2-1
C
2
R
2
C
5
C
4-1
C
4
VS1
0V1
+V1
COM1
-V1
C
6
R
3
C
8
C
7-1
C
7
R
4
C
10
C
9-1
C
9
VS2
0V2
+V2
COM2
-V2
1
2
6
5
7
1
2
6
5
7
14
14
DCP02xP
SYNC
DCP02xP
SYNC
DCP02xU
SYNC
SYNC
JP1
JP2
JP1
JP2
CON1
CON2
CON3
CON4
(1)CapacitorsC ,C ,C ,andC arethrough-holeplatedcomponentsconnectedinparallelwithC ,C ,C ,andC (1206SMD),respectively.
(2)Foroptimumlow-noiseperformance,uselow-ESRcapacitors.
(3)DonotconnecttheSYNCpinjumper(JP1−JP4)iftheSYNCfunctionisnotbeingused.
(4)Connectionstothepowerinputshouldbemadewithaminimumwireof16/0.2twistedpair,withthelengthkeptshort.
(5)VSxand0Vxareinputsupplyandgroundrespectively(xrepresentsthechannel).
(6)+Vxand −Vxarethepositiveandnegativeoutputs,referencedtoacommongroundCOMx.
(7)JPxarethelinksusedforself-synchronization;ifthisfacilityisnotbeingused,thelinksshouldbeunconnected.
(8)R1−R8arethepoweroutputloads;donotfittheseifanexternalloadisconnected.
(9)CON1andCON2areDIL-14;CON3andCON4areSO-28packages.
(10)NC=notconnected.
2−1 4−1 7−1 9−1 2 4 7 9
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
Figure 13. Example of PCB Layout, Schematic Diagram
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