Datasheet

DAC8718
www.ti.com SBAS467A –MAY 2009–REVISED DECEMBER 2009
Offset DAC-A/B Registers (default = 999Ah for dual supplies or 0000h for single supplies).
The Offset DAC-A and Offset DAC-B registers contain, by default, the factory-trimmed Offset DAC code
providing optimal offset and span for symmetric bipolar operation when dual supplies are detected, and contain
code 0000h when a single supply is detected.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
OS15 OS14 OS13 OS12 OS11 OS10 OS9 OS8 OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0
OS15:0 For dual-supply operation, the default code for a gain of 6 is 999Ah with a ±10 LSB variation,
depending on the linearity of each Offset DAC. The default code for a gain of 4 is AAABh with a
±10 LSB variation. The default codes of Offset DAC-A and Offset DAC-B registers are
independently factory trimmed for both gains of 6 and 4.
When single-supply operation is present, writing to these registers is ignored and reading returns
0000h. When dual-supply operation is present, updating the GAIN-A (GAIN-B) bit on the
configuration register automatically reloads the factory-trimmed code into the Offset DAC-A (Offset
DAC-B) register for the new GAIN-A (GAIN-B) setting. See the Offset DACs for further details.
BLANKSPACE
SPI MODE Register (default = 0000h).
The SPI Mode Register is used to put the device into SPI sleep mode.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SLEEP X X X X X X X X X X X X X X X
SLEEP Set the SLEEP bit to '1' to put the device into SPI sleep mode.
When the SLEEP bit = '0', the SPI is in normal mode. The bit is cleared ('0') after a hardware reset
(through the RST pin) or if the WAKEUP pin is low.
For normal SPI operation, the data entering the SDI pin is transferred into the Shift Register.
However, for SPI sleep mode, the Shift Register is bypassed. The data entering into the SDI pin
are directly transferred to the SDO pin instead of the Shift Register.
BLANKSPACE
Broadcast Register.
The DAC8718 broadcast register can be used to update all eight DAC register channels simultaneously using
data bits D15:D0. This write-only register uses address A4:A0 = 07h, and is only available when the SCE bit = '0'
(default). If the SCE bit = '1', this register is ignored. Reading this register always returns 0000h.
BLANKSPACE
Input Data Register for DAC-n, where n = 0 to 7 (default = 0000h).
This register stores the DAC data written to the device when the SCE bit = '1' and is controlled by the correction
engine. When the SCE bit = '0' (default), the DAC Data Register stores the DAC data written to the device. When
the data are loaded into the corresponding DAC latch, the DAC output changes to the new level defined by the
DAC latch. The default value after power-on or reset is 0000h.
Table 13. DAC-n
(1)
Input Data Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB15
(2)
DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(1) n = 0, 1, 2, 3, 4, 5, 6, or 7.
(2) DB15:DB0 are the DAC data bits.
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