Datasheet

SCLK
SYNC
DIN DB31 DB0
LDAC
(1)
LDAC
(2)
CLR
t
2
t
7
t
6
t
9
t
10
t
8
t
4
t
5
t
3
t
1
t
12
t
14
t
15
t
13
t
11
DAC7568
DAC8168
DAC8568
www.ti.com SBAS430D –JANUARY 2009–REVISED MAY 2012
TIMING DIAGRAM
(1) Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section.
(2) Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section.
Figure 1. Serial Write Operation
TIMING REQUIREMENTS
(1) (2)
At AV
DD
= 2.7V to 5.5V and over –40°C to +125°C (unless otherwise noted).
DAC7568/DAC8168/DAC8568
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SCLK falling edge to SYNC falling edge (for
t
1
AV
DD
= 2.7V to 5.5V 10 ns
successful write operation)
t
2
SCLK cycle time AV
DD
= 2.7V to 5.5V 20 ns
(3)
SYNC rising edge to 31st SCLK falling edge AV
DD
= 2.7V to 5.5V 13
t
3
ns
(for successful SYNC interrupt)
t
4
Minimum SYNC HIGH time AV
DD
= 2.7V to 5.5V 80 ns
t
5
SYNC to SCLK falling edge setup time AV
DD
= 2.7V to 5.5V 13 ns
t
6
SCLK LOW time AV
DD
= 2.7V to 5.5V 8 ns
t
7
SCLK HIGH time AV
DD
= 2.7V to 5.5V 8 ns
t
8
SCLK falling edge to SYNC rising edge AV
DD
= 2.7V to 5.5V 10 ns
t
9
Data setup time AV
DD
= 2.7V to 5.5V 6 ns
t
10
Data hold time AV
DD
= 2.7V to 5.5V 4 ns
SCLK falling edge to LDAC falling edge for
t
11
AV
DD
= 2.7V to 5.5V 40 ns
asynchronous LDAC update mode
t
12
LDAC pulse width LOW time AV
DD
= 2.7V to 5.5V 80 ns
LDAC falling edge to SCLK falling edge for
t
13
AV
DD
= 2.7V to 5.5V 4 × t
1
ns
synchronous LDAC update mode
t
14
32nd SCLK falling edge to LDAC rising edge AV
DD
= 2.7V to 5.5V 40 ns
t
15
CLR pulse width LOW time AV
DD
= 2.7V to 5.5V 80 ns
(1) All input signals are specified with t
R
= t
F
= 3ns (10% to 90% of AV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See the Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at AV
DD
= 2.7V to 5.5V.
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Product Folder Link(s): DAC7568 DAC8168 DAC8568