Datasheet
DAC7568
DAC8168
DAC8568
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SBAS430D –JANUARY 2009–REVISED MAY 2012
Flexible Mode (see Table 4, Table 5, and Table 6)
performing a power cycle to reset the device, the
internal reference is switched off (default mode). In
Enabling Internal Reference:
the default mode, the internal reference is powered
Method 1) To enable the internal reference, write the down until a valid write sequence is applied to power
32-bit serial command shown in Table 4. When up the internal reference. When the internal reference
performing a power cycle to reset the device, the is powered up, it remains powered up, regardless of
internal reference is switched off (default mode). In the state of the DACs.
the default mode, the internal reference is powered
Disabling Internal Reference:
down until a valid write sequence is applied to power
up the internal reference. If the internal reference is
To disable the internal reference, write the 32-bit
powered up, it automatically powers down when all
serial command shown in Table 6. When performing
DACs power down in any of the power-down modes
a power cycle to reset the device, the internal
(see the Power Down Modes section). The internal
reference is switched off (default mode).
reference powers up automatically when any DAC is
When the internal reference is operated in Flexible
powered up.
mode, Static mode is disabled and does not work. To
Method 2) To always enable the internal reference,
switch from Flexible mode to Static mode, use the
write the 32-bit serial command shown in Table 5.
command shown in Table 7.
When the internal reference is always enabled, any
power-down command to the DAC channels does not
change the internal reference operating mode. When
Table 4. Write Sequence for Enabling Internal Reference (Flexible Mode)
(Internal Reference Powered On—09080000h)
DB31 DB27 DB23 DB19 DB4 DB0
0 X X X
C3
C2
C1
C0
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F3
F2
F1
F0
0 X X X 1 0 0 1 X X X X 1 0 0 X X X X X X X X X X X X X X X X X
|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |
Table 5. Write Sequence for Enabling Internal Reference (Flexible Mode)
(Internal Reference Always Powered On—090A0000h)
DB31 DB27 DB23 DB19 DB4 DB0
0 X X X
C3
C2
C1
C0
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F3
F2
F1
F0
0 X X X 1 0 0 1 X X X X 1 0 1 X X X X X X X X X X X X X X X X X
|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |
Table 6. Write Sequence for Disabling Internal Reference (Flexible Mode)
(Internal Reference Always Powered Down—090C0000h)
DB31 DB27 DB23 DB19 DB4 DB0
0 X X X
C3
C2
C1
C0
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F3
F2
F1
F0
0 X X X 1 0 0 1 X X X X 1 1 0 X X X X X X X X X X X X X X X X X
|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |
Table 7. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference
(Internal Reference Always Powered Down—09000000h)
DB31 DB27 DB23 DB19 DB4 DB0
0 X X X
C3
C2
C1
C0
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
F3
F2
F1
F0
0 X X X 1 0 0 1 X X X X 0 0 0 X X X X X X X X X X X X X X X X X
|-- Prefix Bits --| |- Control Bits -| | Address Bits | |-------------------------------------- Data Bits --------------------------------------| | Feature Bits |
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