Datasheet

DAC8565
V A
OUT
V B
OUT
V H/V OUT
REF REF
AV
DD
LDAC
ENABLE
RSTSEL
RST
1
2
3
4
16
15
14
13
V L
REF
GND
V
OUT
C
5
6
7
V
OUT
D
8
IOV
DD
D
IN
12
11
10
SCLK
SYNC
9
DAC8565
www.ti.com SBAS411C –JUNE 2007–REVISED MARCH 2011
PIN CONFIGURATIONS
PW PACKAGE
TSSOP-16
(Top View)
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1 V
OUT
A Analog output voltage from DAC A
2 V
OUT
B Analog output voltage from DAC B
V
REF
H/
3 Positive reference input / reference output 2.5V if internal reference used.
V
REF
OUT
4 AV
DD
Power-supply input, 2.7V to 5.5V
5 V
REF
L Negative reference input
6 GND Ground reference point for all circuitry on the part
7 V
OUT
C Analog output voltage from DAC C
8 V
OUT
D Analog output voltage from DAC D
Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output
9 SYNC
updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as
an interrupt, and the write sequence is ignored by the DAC8565. Schmitt-Trigger logic Input.
10 SCLK Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic Input.
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.
11 D
IN
Schmitt-Trigger logic Input.
12 IOV
DD
Digital input-output power supply
Asynchronous reset. Active low. If RST is low, all DAC channels reset either to zero-scale (RSTSEL = 0) or to
13 RST
midscale (RSTSEL = 1).
14 RSTSEL Reset select. If RSTSEL is low, input coding is binary; if high = two's complement.
15 ENABLE The enable pin (active low) connects the SPI interface to the serial port
16 LDAC Load DACs; rising edge triggered, loads all DAC registers
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): DAC8565