Information

Texas Instruments Signal Chain Guide 2013 | 93
Control
Output
PLLInput
N
8-b,10-b
R
4-b
Host
Interface
Status/
Monitoring
Power
Conditioning
CDCM6208
Differential/
LVCMOS
LVCMOS/XTAL
Differential
LVPECL/
CML/
LVDS
LVDS/
LVCMOS/
HCSL
Fractional Div
M
0
14-b
Integer Div
LVDS/
LVCMOS/
HCSL
VCO:
V1: (2.39-2.55) GHz
and V2
: ( 2.94-3.13) GHz
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
PRI _REF
SEC
_ REF
Integer Div
PreScaler PS_A
÷4, ÷5, ÷6
ELF
REF SEL_
Smat MUX
Fractional Div
Fractional Div
Fractional Div
20-b
20-b
8-b
8-b
20-b
20-b
PreScaler PS_B
÷4, ÷5, ÷6
Clocks and Timing
Clock Generation (Crystal Oscillator Replacements, Jitter Cleaners)
Clock Generator/Jitter Cleaner with Internal VCO Output
CDCM6208
Ultra-Low Jitter Synthesizer and Jitter Cleaner
LMK04828
Key Features
• Superiorperformancewithlowpower
• Flexiblefrequencyplanning
• Twodifferentialinputs,XTALsupport,
ability for smart switching
•
SPI,I
2
C, and pin programmable
• ProfessionaluserGUIforquickdesign
turnaround
•
7×7mm48-QFNpackage(RGZ)
• –40°Cto85°Ctemperaturerange
Applications
• Basebandclocking
(Wireless Infrastructure)
•
Networkinganddatacommunications
• Keystone
TM
C66x multicore DSP
clocking
• Storageserver;portabletest
equipment
•
Medicalimaging;highendA/V
Key Features
• JEDECJESD204Bsupport
Seven device clocks and up to seven
SYSREF clocks
Up to 14 differential device clocks
LVPECL, LVDS, or HSDS program-
mable outputs
•
Ultra-lowRMSjitterperformance
• DualloopPLLatinumPLLarchitecture
• TworedundantinputclockswithLOS
• Multi-mode:DualPLL,singlePLL,and
clock distribution
• Industrialtemperaturerange:–40to85°C
• 3.15Vto3.45Voperation
• Package:64-pinLLP
(9.0
×9.0×0.8mm)
The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which
can generate eight low jitter clock outputs, selectable from one of two inputs that
can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for
a variety of wireless infrastructure baseband, wireline data communication, comput-
ing, low power medical imaging and portable test and measurement applications. The
CDCM6208 also featur
es a fractional divider architecture for four of its outputs that can
generate any frequency with better than one ppm frequency accuracy. The CDCM6208
can be easily configured through I
2
C or SPI programming interface and in the absence
of serial interface, pin mode is also available that can set the device in 1 of 32 distinct
pre-programmed configurations using control pins.
The LMK04820 family is the industry’s highest performance clock conditioner with
JEDEC JESD204B support. The dual loop PLLatinum
TM
architecture enables sub-100
fs RMS jitter (10 kHz to 20 MHz) using a low noise VCXO module.
The dual loop architecture consists of two high-performance phase-locked loops (PLL), a
low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO).
The LMK04828 provides ultra-low-jitter and phase noise and generates the JESD204B
system timing reference signal (SYSREF) required for multi-device synchronization.
CDCM6208 functional block diagram
LMK04828 functional block diagram
Get more information: www.ti.com/product/CDCM6208
Get more information:
www.ti.com/product/LMK04828
R
CLKinX
CLKinX*
N
Phase
Detector
PLL1
External VCXO
or Tunable
Crystal
R
N
Phase
Detector
PLL2
Internal
VCO
External
Loop Filter
OSC in
CPout 1
OSCout
OSCout *
LMK04828
CPout2
Device Clock
Divider
Digital Delay
Analog Delay
SDCLKoutY
SDCLKoutY*
DCLKoutX
DCLKoutX*
Partially
Integrated
Loop Filter
6 Device
Clocks
External
Loop Filter
PLL1 PLL2
6 blocks
2 inputs
Input
Buffer
SYSREF
Digital Delay
Analog Delay
6 SYSREF
or Device
Clocks
1 Global SYSREF Divider
Applications
• JEDECJESD204B
• Wirelessinfrastructure
• Dataconverterclocking
• Networking,SONET/SDH,DSLAM
• Medical/video/military/aerospace
• Testandmeasurement