Information
114 | Signal Chain Guide 2013 Texas Instruments
Interface
Consumer/Computing – Flatlink
™
/FPD-LINK
Get more information: www.ti.com/product/SN65LVDS324
High Definition Image Sensor Receiver
SN65LVDS324
The SN65LVDS324 is a SubLVDS deserializer that recovers words, detects sync codes,
multiplies the input DDR clock by a ratio, and outputs parallel CMOS 1.8 V data on
the rising clock edge. It bridges the video stream interface between HD image sensors
made by leading manufacturers, to a format that common processors can accept. The
supported pixel frequency is 18.5 MHz to 162 MHz — suitable for resolutions from VGA
to1080p60.Withintegrateddifferentialinputtermination,andafootprintof4.5×7mm,
the SN65LVDS324 provides a differentiated solution with optimized form, function, and
cost. It operates through an ambient temperature range of –40°C to 85°C.
SN65LVDS324 functional block diagram
Key Features
• Bridgestheinterfacebetweenvideo
image sensors and processors
• Outputs1.8VCMOSwith10-/12-/14-
/16-bits at 18.5 MHz to 162 MHz
• SubLVDSinputssupportupto648
Mbps
• Integrated100Ωdifferentialinput
termination
• Testimagegenerationfeature
• CompatiblewithTIOMAP™and
DaVinci™ Including DM385, DM8127,
DM36x, and DMVA
• Lowpower1.8VCMOSprocess
• Configurableoutputconventions
• Packagedin4.5×7mmBGA
Applications
• IPnetworkcameras
• Machinevision
• Videoconferencing
• Gesturerecognition
FlatLink™/FPD-LINK LVDS Receivers and Transmitters
Device
Description
Parallel
Inputs or
Outputs
Serial
Chs.
Data
Throughput
(Mbps)
PLL
Frequency
(MHz)
Supply
Voltage
(V)
HiRel
Avail. Package Price*
FlatLink LVDS Receiver
SN65LVDS324
High Definition Image Sensor Receiver 18 12 324 18 to 162 1.8
N
59BGA MicroStar Junior™ 2.65
SN75LVDS86A
FlatLink Receiver 21 3 1428 32 to 68 3.3
N
TSSOP-48 2.40
SN75LVDS82
FlatLink Receiver 28 4 1904 31 to 68 3.3
N
TSSOP-56 2.45
DS90CF386
FPD-Link (FlatLink) Receiver 28 4 2380 20 to 85 3.3
N
TSSOP-56 3.26
DS90CF388
Dual FPD-Link (FlatLink) Receiver 51 8 5712 40 to 112 3.3
N
TQFP-100 4.91
DS90C3202
Dual FPD-Link (FlatLink) Receiver 70 10 9450 8 to 135 3.3
N
TQFP-128 3.80
DS90CR216A
Rising Edge Data Strobe Channel Link 21 3 1386 20 to 66 3.3
N
TSSOP-48 2.48
DS90CR218A
Rising Edge Data Strobe Channel Link 21 3 1785 12 to 85 3.3
N
TSSOP-48 2.60
DS90CR286A
Rising Edge Data Strobe Channel Link 28 4 1848 20 to 66 3.3
Y
TSSOP-56 3.32
DS90CR288A
Rising Edge Data Strobe Channel Link 28 4 2380 20 to 85 3.3
N
TSSOP-56 4.20
DS90CR484A
Rising Edge Data Strobe Channel Link 48 8 5376 33 to 112 3.3
N
TQFP-100 8.06
DS90CR486
Rising Edge Data Strobe Channel Link 48 8 6384 66 to 133 3.3
N
TQFP-100 9.28
*Suggested resale price in U.S. dollars in quantities of 1,000. See www.ti.com/hirel for HiRel options. New products are listed in bold red.
HD
Image
Sensor
Video
Processor
SubLVDS data
SubLVDS clock
10 to 16-bit data
Vsync/Hsync
Clock
I
2
CI
2
C or SPI
SN65LVDS324
• De-serialize
• Recover words
• Decode syncs
• Multiply clock