Datasheet

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THEORY OF OPERATION
DAC SECTION
GND
DAC
Register
V
REF
V
OUT
50kW
62kW
50kW
REF(+)
RegisterString
REF( )-
V
FB
V
OUT
+
D
IN
65536
V
REF
(1)
RESISTOR STRING
V
REF
R
R
R
R
V
REF
2
R
DIVIDER
ToOutputAmplifier
(2xGain)
SERIAL INTERFACE
OUTPUT AMPLIFIER
DAC8551
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
The DAC8551 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 45
shows a block diagram of the DAC architecture.
Figure 45. DAC8551 Architecture
The input coding to the DAC8551 is straight binary,
so the ideal output voltage is given by:
where D
IN
= decimal equivalent of the binary code
that is loaded to the DAC register; it can range from
0 to 65535.
The resistor string section is shown in Figure 46 . It is
simply a string of resistors, each of value R. The
Figure 46. Resistor String
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier.
Monotonicity is ensured because of the string
The DAC8551 has a 3-wire serial interface ( SYNC,
resistor architecture.
SCLK, and D
IN
), which is compatible with SPI, QSPI,
and Microwire interface standards, as well as most
DSPs. See the Serial Write Operation Timing
Diagram for an example of a typical write sequence.
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving an output The write sequence begins by bringing the SYNC
range of 0V to V
DD
. It is capable of driving a load of line LOW. Data from the D
IN
line are clocked into the
2k Ω in parallel with 1000pF to GND. The source and 24-bit shift register on each falling edge of SCLK.
sink capabilities of the output amplifier can be seen The serial clock frequency can be as high as 30MHz,
in the Typical Characteristics . The slew rate is making the DAC8551 compatible with high-speed
1.8V/ µ s with a full-scale setting time of 8 µ s with the DSPs. On the 24th falling edge of the serial clock,
output unloaded. the last data bit is clocked in and the programmed
function is executed (that is, a change in DAC
The inverting input of the output amplifier is brought
register contents and/or a change in the mode of
out to the V
FB
pin. This configuration allows for better
operation).
accuracy in critical applications by tying the V
FB
point
and the amplifier output together directly at the load.
Other signal conditioning circuitry may also be
connected between these points for specific
applications.
15
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