Datasheet

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UPDATE SEQUENCE

READBACK

RST

POWER-ON RESET

POWER-DOWN MODES

DAC8544

SLAS420A – MAY 2004 – REVISED JUNE 2005

For regular operation, R/ W pin should be kept low while CS is kept high. Then, the 16-bit digital data should be

applied to the input bus. The channel selection should then be asserted by setting the A0 and A1 pins. Once the

data is stable and the channels are selected the falling edge of CS enables the device and latches the data to

the input register of the selected channel. After the data is latched to the input register, the rising edge of the

LDAC signal updates all four channels simultaneously with existing data from their corresponding input register.

Table 3. Update Sequence Section

A1 A0 CS R/W LDAC ACTION

0 0 ↓ L X Latches external data into the DAC A input register.

0 1 ↓ L X Latches external data into the DAC B input register.

1 0 ↓ L X Latches external data into the DAC C input register.

1 1 ↓ L X Latches external data into the DAC D input register.

For read-back operation, the user first releases the 16-bit bus, while CS is high. Then, the DAC channel should

be selected using the A0 and A1 pins. R/ W pin is then brought high to enable read-back operation. Following the

falling edge of CS, the data from the selected channel (buffer data) is output on the bus.

Table 4. Readback Section

A1 A0 CS R/W ACTION

0 0 ↓ H DAC A input register data is presented to the data bus.

0 1 ↓ H DAC B input register data is presented to the data bus.

1 0 ↓ H DAC C input register data is presented to the data bus.

1 1 ↓ H DAC D input register data is presented to the data bus.

The RST input controls the reset of the DAC register and, consequently, the DAC output, but does not change

the input register. The reset operation is edge-triggered by a low-to-high transition on the RST pin. Once a rising

edge on RST is detected, the DAC output settles to the zero code. Application of a valid reset signal to the DAC

does not overwrite existing data in the input register.

The DAC8544 contains a power-on reset circuit that controls the output voltage after power up. On power up, the

DAC register (and DAC output) is set to zero (plus a small offset error produced by the output buffer). It remains

at zero until a valid write sequence is made to the DAC, changing the DAC register data. This is useful in

applications where it is important to know the state of the output of the DAC after power up. All digital inputs

must be logic low until the digital and analog supplies are applied. Logic high voltages, applied to the input pins

when power is not applied to IOV

and V

, may power the device through the ESD input structures causing

undesired operation.

The DAC8544 uses two modes of operation. These modes are programmable via pin PD.

Table 5 shows how the state of the pin correspond to the mode of operation of the DAC8544.

Table 5. Modes of Operation for the DAC8544

PD OPERATING MODE

High Normal operation

Low Power down, high impedance