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EVM Operation

When the shunt on JP6 is moved to pins 2-3, a user-provided GPIO input may be applied to the LDAC pin

via J1.15. This external input acts as an interrupt input to a DSP host processor which can in turn trigger a

serial transfer to the DAC. JP2 can be used to hold the LDAC input to the DAC at ground potential if

synchronous updates are required.

5.6 CLEAR (CLR)

Jumper JP1 is provided to allow the manual application of a CLR input pulse. The DACxx68EVM user

may also apply a CLR input via J1 pin 19. Bringing the CLR pin low clears the content of all DAC registers

and all DAC buffers, and replaces the code with the code determined by the clear code register. Jumper

JP1 is open by default and uses a 10-kΩ pullup resistor (R1) to maintain logic high on the CLR input pin.

5.7 Default Jumper Locations

Table 3 provides a list of jumpers found on the EVM and their factory default conditions.

Table 3. EVM Default Jumper Settings

Jumper Shunt Position Jumper Description

Allows CLR to be monitored or controlled via external pulse source. Used with signals applied to

JP1 N/A

J1.19

Allows LDAC to be kept at GND potential when installed; it is recommended to remove any

JP2 OPEN

shunt jumper installed on JP6 if JP1 is installed.

Controls reference voltage applied to the installed DAC. When JP3 is moved to pins 2-3, and

JP3 Pins 1-2

external reference may be applied to the EVM via J2.20 or to TP3 referenced to TP2

Analog power source control. Default is from J3.3. When shunt is placed on pins 2-3, power to

JP4 Pins 1-2

the DAC may be applied to TP1 referenced to TP4.

JP5 Pins 1-2 Controls SYNC source selection – see Section 5.3 for details

JP6 Pins 1-2 Controls LDAC source selection – see Section 5.4 for details

The following diagram provides an overview of the DACxx68 assembly and locations of the various

jumpers and connectors.

Figure 1. Top Layer Assembly Drawing and Jumper Locations

SLAU301–November 2009 DACxx68EVM

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