Datasheet

®
14
DAC7714
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
DS
Data Valid to CLK Rising 25 ns
t
DH
Data Held Valid after CLK Rises 20 ns
t
CH
CLK HIGH 30 ns
t
CL
CLK LOW 50 ns
t
CSS
CS LOW to CLK Rising 55 ns
t
CSH
CLK HIGH to CS Rising 15 ns
t
LD1
LOADDACS HIGH to CLK Rising 40 ns
t
LD2
CLK Rising to LOADDACS LOW 15 ns
t
LDDW
LOADDACS LOW Time 45 ns
t
RSSH
RESETSEL Valid to RESET LOW 25 ns
t
RSTW
RESET LOW Time 70 ns
t
S
Settling Time 10 µs
FIGURE 4. DAC7714 Timing.
TABLE I. Timing Specifications (T
A
= –40°C to +85°C).
A1
(MSB) (LSB)
SDI
CLK
CS
LOADDACS
A0 X X D11 D10 D9 D3 D2 D1 D0
SDI
CLK
LOADDACS
RESET
V
OUT
t
css
t
LD1
t
CL
t
CH
t
DS
t
DH
t
LD2
t
LDDW
t
LDDW
t
S
t
RSTW
t
RSSH
t
CSH
t
S
1 LSB
ERROR BAND
1 LSB
ERROR BAND
RESETSEL
STATE OF
SELECTED SELECTED
DAC DAC
A1 A0 LOADDACS RESET REGISTER REGISTER
L
(1)
LLH
(2)
A Transparent
L H L H B Transparent
H L L H C Transparent
H H L H D Transparent
X
(3)
X H H NONE (All Latched)
X X X L ALL Reset
(4)
NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care.
(4) Resets to either 000H or 800
H
, per the RESETSEL state
(LOW = 000
H
, HIGH = 800
H
). When RESET rises, all registers that are in
their latched state retain the reset value.
TABLE II. Control Logic Truth Table.