Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) USON 12

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FEATURES DESCRIPTION

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

Interface

Logic

Shift

DAC

String

DAC

Power-Down

Logic

Power-On

Reset

IOV

REF

OUT

REF

LGNDCLR

SDO

SDIN

SYNC

SCLK

DAC7551

SLAS441E – MARCH 2005 – REVISED APRIL 2007

12-Bit, Ultra-Low Glitch, Voltage Output

DIGITAL-TO-ANALOG CONVERTER

• Relative Accuracy (INL): ± 0.35LSB

The DAC7551 is a single-channel, voltage-output

digital-to-analog converter (DAC) with exceptional

• Ultra-Low Glitch Energy: 0.1nV-s

linearity and monotonicity, and a proprietary

• Low Power Operation: 100 µ A at 2.7V

architecture that minimizes glitch energy. The

• Power-On Reset to Zero Scale

low-power DAC7551 operates from a single 2.7V to

• Power Supply: 2.7V to 5.5V Single Supply 5.5V supply. The DAC7551 output amplifiers can

drive a 2k Ω , 200pF load rail-to-rail with 5 µ s settling

• Power-Down: 0.05 µ A at 2.7V

time; the output range is set using an external

• 12-Bit Linearity and Monotonicity

voltage reference.

• Rail-to-Rail Voltage Output

The 3-wire serial interface operates at clock rates up

• Settling Time: 5 µ s (Max)

to 50MHz and is compatible with SPI™, QSPI™,

• SPI-Compatible Serial Interface with Microwire™, and DSP interface standards. The parts

incorporate a power-on-reset circuit to ensure that

Schmitt-Trigger Input: Up to 50MHz

the DAC output powers up to 0V and remains there

• Daisy-Chain Capability

until a valid write cycle to the device takes place. The

• Asynchronous Hardware Clear to Zero Scale

part contains a power-down feature that reduces the

current consumption of the device to under 2 µ A.

• Specified Temperature Range:

– 40 ° C to +105 ° C

Small size and low-power operation make the

• Small, 2 x 3 mm, 12-Lead SON Package

DAC7551 ideally suited for battery-operated, portable

applications. The power consumption is typically

0.5mW at 5V, 0.23mW at 3V, and reduces to 1 µ W in

power-down mode.

• Portable, Battery-Powered Instruments

• Digital Gain and Offset Adjustment

The DAC7551 is available in a 12-lead SON

package and is specified over –40 ° C to +105 ° C.

• Programmable Voltage and Current Sources

• Programmable Attenuators

• Industrial Process Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI, QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corp..

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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DAC7551 SLAS441E – MARCH 2005 – REVISED APRIL 2007 12-Bit, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • • DESCRIPTION Relative Accuracy (INL): ±0.35LSB Ultra-Low Glitch Energy: 0.1nV-s Low Power Operation: 100µA at 2.7V Power-On Reset to Zero Scale Power Supply: 2.7V to 5.5V Single Supply Power-Down: 0.05µA at 2.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 ELECTRICAL CHARACTERISTICS all specifications at –40°C to +105°C, VDD = 2.7V to 5.5V, VREFH = VDD, VREFL = GND, RL = 2kΩ to GND, and CL = 200pF to GND (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ±0.35 ±1 LSB ±0.08 ± 0.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 ELECTRICAL CHARACTERISTICS (continued) all specifications at –40°C to +105°C, VDD = 2.7V to 5.5V, VREFH = VDD, VREFL = GND, RL = 2kΩ to GND, and CL = 200pF to GND (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS VDD 2.7 5.5 V IOVDD (3) 1.8 VDD V IDD (4) Normal operation (DAC active and excluding load current) All power-down modes VDD = 3.6V to 5.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 PIN CONFIGURATION VDD 1 12 IOVDD VREFH 2 11 SDO VREFL 3 10 SDIN 9 SCLK 8 SYNC 7 CLR DAC7751 VFB 4 VOUT 5 GND 6 Thermal Pad(1) Pin Descriptions PIN NO. (1) NAME DESCRIPTION 1 VDD Analog voltage supply input 2 VREFH Positive reference voltage input 3 VREFL Negative reference voltage input 4 VFB DAC amplifier sense input. 5 VOUT Analog output voltage from DAC 6 GND (1) Ground.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 SERIAL WRITE OPERATION t1 SCLK t8 t2 t3 t4 t7 SYNC t5 SDIN t6 D15 D14 D13 D12 D11 D1 D0 Input Word n D15 D0 t9 SDO Input Word n+1 D15 D0 D14 Input Word n Undefined t10 CLR Figure 1. Serial Write Operation Timing Diagram TIMING CHARACTERISTICS (1) (2) All specifications at –40°C to +105°C, VDD = 2.7V to 5.5V, and RL = 2kΩ to GND (unless otherwise noted).
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 VDD = 5V, VREFH = 4.096V, VREFL = GND 0.5 LE (LSB) LE (LSB) 1.0 0 -1.0 -1.0 0.50 0.50 0.25 0.25 0 -0.25 -0.50 512 1024 1536 2048 2560 3072 3584 -0.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 5.5 0.20 VDD = VREFH = 5.5V 0.15 Output Voltage, VO (V) Output Voltage, VO (V) Typical VDD = 2.7V VREFH = 2.5V VREFL = GND 0.10 VDD = 5.5V VREFH = 4.096V VREFL = GND 0.05 VREFL = GND 5.4 5.3 DAC Loaded with FFFFh DAC Loaded with 0000h 5.2 0 0 5 10 0 15 5 Figure 9.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION - 5.5V 2000 1600 TA = +25°C SCLK Input All Other Input = GND 1500 VDD = 5.5V VREFH = 4.096V VREFL = GND 800 Frequency (Hz) IDD (mA) 1200 1000 VDD = 2.7V VREFH = 2.5V VREFL = GND 400 Digital Input Code = 2048 VDD = 5.5V VREFH = 4.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. LARGE-SIGNAL SETTLING TIME - 5V Output Loaded with 200pF to GND Code 0041 to 4055 4 3 LARGE-SIGNAL SETTLING TIME - 2.7V 3 Output Voltage, VO (V) Output Voltage, VO (V) 5 VDD = 5V VREFH = 4.096V VREFL = GND 2 1 0 Output Loaded with 200pF to GND Code 0041 to 4055 2 VDD = 2.7V VREFH = 2.5V VREFL = GND 1 0 Time (5ms/div) Figure 20. Figure 21.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER VREFH The architecture of the DAC7551 consists of a string DAC followed by an output buffer amplifier. Figure 26 shows a generalized block diagram of the DAC architecture. VREFH 100kW RDIVIDER VREFH - VREFL 2 100kW R VFB 50kW DAC Register VOUT REF(+) Resistor String REF(-) R To Output Amplifier (2x Gain) VREFL Figure 26.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 OUTPUT BUFFER AMPLIFIERS The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0V to VDD. It is capable of driving a load of 2kΩ in parallel with up to 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1.8V/µs with a half-scale settling time of 3µs with the output unloaded.
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DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 SERIAL INTERFACE The DAC7551 is controlled over a versatile 3-wire serial interface, which operates at clock rates up to 50MHz and is compatible with SPI, QSPI, Microwire, and DSP interface standards. 16-Bit Word and Input Shift Register The input shift register is 16 bits wide. DAC data are loaded into the device as a 16-bit word under the control of a serial clock input, SCLK, as shown in Figure 1, the Serial Write Operation timing diagram.
PAGE 14
DAC7551 www.ti.com SLAS441E – MARCH 2005 – REVISED APRIL 2007 APPLICATION INFORMATION WAVEFORM GENERATION As a result of the exceptional linearity and low glitch of the DAC7551, the device is well-suited for waveform generation (from DC to 10kHz). The DAC7551 large-signal settling time is 5µs, supporting an update rate of 200kSPS. However, the update rates can exceed 1MSPS if the waveform to be generated consists of small voltage steps between consecutive DAC updates.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7551IDRNR USON DRN 12 3000 330.0 12.4 2.3 3.3 0.85 4.0 12.0 Q1 DAC7551IDRNT USON DRN 12 250 180.0 12.4 2.3 3.3 0.85 4.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7551IDRNR USON DRN 12 3000 338.1 338.1 20.6 DAC7551IDRNT USON DRN 12 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.