Datasheet

DAC3484
SLAS749C –MARCH 2011–REVISED AUGUST 2012 www.ti.com
Table 2. Register Map
(1)
(MSB) (LSB)
Name Address Default Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 15 Bit 0
qmc_ qmc_ qmc_ qmc_
alarm_out_ alarm_out clkdiv_ invsincAB_ invsincCD_
config0 0x00 0x049C offsetAB_ offsetCD_ corrAB_ corrCD_ interp(3:0) fifo_ena reserved reserved
ena pol sync_ ena ena ena
ena ena ena ena
word_ frame_ alarm_ alarm_ alarm_
64cnt_
oddeven_ dacA_ dacB_ dacC_ dacD_
config1 0x01 0x050E iotest_ena reserved reserved parity_ parity_ quad_ena 2away_ 1away_ collision_ reserved
parity complement complement complement complement
ena
ena ena ena ena ena
dacclk dataclk collision_
config2 0x02 0x7000 16bit_in reserved reserved reserved reserved sif4_ena mixer_ena mixer_gain nco_ena revbus reserved twos reserved
gone_ena gone_ena gone_ena
config3 0x03 0xF000 coarse_dac(3:0) reserved reserved sif_txenable
config4 0x04 NA iotest_results(15:0)
alarm_ alarm_
alarm_ alarm_ alarm_
alarm_
alarm_
alarm_ alarm_
dacclk_ dataclk_ output_
config5 0x05 0x0000 from_ reserved alarms_from_fifo(2:0) from_ reserved frame_ reserved reserved
from_pll rparity
fparity
parity
gone gone gone
zerochk iotest
config6 0x06 NA tempdata(7:0) reserved reserved reserved
config7 0x07 0xFFFF alarms_mask(15:0)
config8 0x08 0x0000 reserved reserved reserved qmc_offsetA(12:0)
config9 0x09 0x8000 fifo_offset(2:0) qmc_offsetB(12:0)
config10 0x0A 0x0000 reserved reserved reserved qmc_offsetC(12:0)
config11 0x0B 0x0000 reserved reserved reserved qmc_offsetD(12:0)
config12 0x0C 0x0400 reserved reserved reserved reserved reserved qmc_gainA(10:0)
config13 0x0D 0x0400 cmix(3:0) reserved qmc_gainB(10:0)
config14 0x0E 0x0400 reserved reserved reserved reserved reserved qmc_gainC(10:0)
config15 0x0F 0x0400 output_delayAB (1:0) output_delayCD (1:0) reserved qmc_gainD(10:0)
config16 0x10 0x0000 reserved reserved dual_ena (1:0) qmc_phaseAB(11:0)
config17 0x11 0x0000 reserved reserved reserved reserved qmc_phaseCD(11:0)
config18 0x12 0x0000 phase_offsetAB(15:0)
config19 0x13 0x0000 phase_offsetCD(15:0)
config20 0x14 0x0000 phase_addAB(15:0)
config21 0x15 0x0000 phase_addAB(31:16)
config22 0x16 0x0000 phase_addCD(15:0)
config23 0x17 0x0000 phase_addCD(31:16)
pll_
config24 0x18 NA reserved pll_reset ndivsync_ pll_ena reserved pll_cp(1:0) pll_p(2:0) pll_lfvolt(2:0)
ena
config25 0x19 0x0440 pll_m(7:0) pll_n(3:0) pll_vcoitune(2:0) reserved
bias_ tsense_ clkrecv_
config26 0x1A 0x0020 pll_vco(5:0) reserved reserved pll_sleep sleepA sleepB sleepC sleepD
sleep sleep sleep
extref_ fuse_
config27 0x1B 0x0000 reserved reserved reserved reserved reserved reserved reserved reserved reserved
ena sleep
config28 0x1C 0x0000 reserved reserved
config29 0x1D 0x0000 reserved reserved
config30 0x1E 0x1111 syncsel_qmoffsetAB(3:0) syncsel_qmoffsetCD(3:0) syncsel_qmcorrAB(3:0) syncsel_qmcorCD(3:0)
(1) Unless otherwise noted, all reserved registers should be programmed to default values.
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