Datasheet

DAC128S085
www.ti.com
SNAS407F AUGUST 2007REVISED MARCH 2013
Electrical Characteristics (continued)
The following specifications apply for V
A
= +2.7V to +5.5V, V
REF1
= V
REF2
= V
A
, C
L
= 200 pF to GND, f
SCLK
= 30 MHz, input
code range 48 to 4047. Boldface limits apply for T
MIN
T
A
T
MAX
and all other limits are at T
A
= 25°C, unless otherwise
specified.
Limits Units
Symbol Parameter Conditions Typical
(1)
(Limits)
V
A
= 2.7V
0.6 5.4 µW (max)
f
SCLK
= 30 MHz, SYNC =
to 3.6V
V
A
and D
IN
= 0V after PD
V
A
= 4.5V
mode loaded
2.5 16.5 µW (max)
Total Power Consumption in all PD
to 5.5V
P
PD
Modes,
V
A
= 2.7V
(4)
0.3 3.6 µW (max)
f
SCLK
= 0, SYNC = V
A
and
to 3.6V
D
IN
= 0V after PD mode
V
A
= 4.5V
loaded
1 11 µW (max)
to 5.5V
A.C. and Timing Characteristics
The following specifications apply for V
A
= +2.7V to +5.5V, V
REF1,2
= V
A
, C
L
= 200 pF to GND, f
SCLK
= 30 MHz, input code
range 48 to 4047. Boldface limits apply for T
MIN
T
A
T
MAX
and all other limits are at T
A
= 25°C, unless otherwise
specified.
Limits Units
Symbol Parameter Conductions Typical
(1)
(Limits)
f
SCLK
SCLK Frequency 40 30 MHz (max)
Output Voltage Settling Time 400h to C00h code change
t
s
6 8.5 µs (max)
(2)
R
L
= 2k, C
L
= 200 pF
SR Output Slew Rate 1 V/µs
GI Glitch Impulse Code change from 800h to 7FFh 40 nV-sec
DF Digital Feedthrough 0.5 nV-sec
DC Digital Crosstalk 0.5 nV-sec
CROSS DAC-to-DAC Crosstalk 1 nV-sec
MBW Multiplying Bandwidth V
REF1,2
= 2.5V ± 2Vpp 360 kHz
V
REF1,2
= 2.5V ± 0.5Vpp
THD+N Total Harmonic Distortion Plus Noise 80 dB
100Hz < f
IN
< 20kHz
ONSD Output Noise Spectral Density DAC Code = 800h, 10kHz 40 nV/sqrt(Hz)
ON Output Noise BW = 30kHz 14 µV
V
A
= 3V 3 µsec
t
WU
Wake-Up Time
V
A
= 5V 20 µsec
1/f
SCLK
SCLK Cycle Time 25 33 ns (min)
t
CH
SCLK High time 7 10 ns (min)
t
CL
SCLK Low Time 7 10 ns (min)
3 10 ns (min)
SYNC Set-up Time prior to SCLK
t
SS
1 / f
SCLK
-
Falling Edge
ns (max)
3
Data Set-Up Time prior to SCLK Falling
t
DS
1.0 2.5 ns (min)
Edge
Data Hold Time after SCLK Falling
t
DH
1.0 2.5 ns (min)
Edge
0 3 ns (min)
SYNC Hold Time after the 16th falling
t
SH
1 / f
SCLK
-
edge of SCLK
ns (max)
3
t
SYNC
SYNC High Time 5 15 ns (min)
(1) Test limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
(2) This parameter is guaranteed by design and/or characterization and is not tested in production.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DAC128S085