Datasheet

To Output Amplifier

DAC124S085

SNAS348F –MAY 2006–REVISED MARCH 2013

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Figure 29. DAC Resistor String

OUTPUT AMPLIFIERS

The output amplifiers are rail-to-rail, providing an output voltage range of 0V to V

when the reference is V

. All

amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and V

in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the

reference is less than V

, there is only a loss in linearity in the lowest codes. The output capabilities of the

amplifier are described in the Electrical Tables.

The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to V

. The zero-

code and full-scale outputs for given load currents are available in the Electrical Characterisics Table.

REFERENCE VOLTAGE

The DAC124S085 uses a single external reference that is shared by all four channels. The reference pin, V

REFIN

is not buffered and has an input impedance of 30 kΩ. It is recommended that V

REFIN

be driven by a voltage

source with low output impedance. The reference voltage range is 1.0V to V

, providing the widest possible

output dynamic range.

SERIAL INTERFACE

The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs and operates at

clock rates up to 40 MHz. See the Timing Diagram for information on a write sequence.

A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the D

line is clocked

into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register,

it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Serial Timing Diagram,

Figure 2). On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in

the DAC channel address, mode of operation and/or register contents) is executed. At this point the SYNC line

may be kept low or brought high. Any data and clock pusles after the 16th falling clock edge will be ignored. In

either case, SYNC must be brought high for the minimum specified time before the next write sequence is

initiated with a falling edge of SYNC.

Since the SYNC and D

buffers draw more current when they are high, they should be idled low between write

sequences to minimize power consumption.

Product Folder Links: DAC124S085