Datasheet

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SCLK

GND

OUT

SYNC

GND

SCLK

OUT

SYNC

DAC101S101, DAC101S101-Q1

www.ti.com

SNAS321F –JUNE 2005–REVISED MARCH 2013

DAC101S101/DAC101S101Q 10-Bit Micro Power, RRO Digital-to-Analog Converter

Check for Samples: DAC101S101, DAC101S101-Q1

FEATURES

DESCRIPTION

The DAC101S101 is a full-featured, general purpose

• DAC101S101Q is AEC-Q100 Grade 1 Qualified

10-bit voltage-output digital-to-analog converter

and is Manufactured on an Automotive Grade

(DAC) that can operate from a single +2.7V to 5.5V

Flow.

supply and consumes just 175 µA of current at 3.6

• Ensured Monotonicity

Volts. The on-chip output amplifier allows rail-to-rail

output swing and the three wire serial interface

• Low Power Operation

operates at clock rates up to 30 MHz over the

• Rail-to-Rail Voltage Output

specified supply voltage range and is compatible with

• Power-on Reset to Zero Volts Output

standard SPI, QSPI, MICROWIRE and DSP

• Wide Temperature Range of −40°C to +125°C

interfaces. Competitive devices are limited to 20 MHz

clock rates at supply voltages in the 2.7V to 3.6V

• Wide Power Supply Range of +2.7V to +5.5V

range.

• Small Packages

The supply voltage for the DAC101S101 serves as its

• Power Down Feature

voltage reference, providing the widest possible

output dynamic range. A power-on reset circuit

APPLICATIONS

ensures that the DAC output powers up to zero volts

and remains there until there is a valid write to the

• Battery-Powered Instruments

device. A power-down feature reduces power

• Digital Gain and Offset Adjustment

consumption to less than a microWatt.

• Programmable Voltage & Current Sources

The low power consumption and small packages of

• Programmable Attenuators

the DAC101S101 make it an excellent choice for use

• Automotive

in battery operated equipment.

The DAC101S101 is a direct replacement for the

KEY SPECIFICATIONS

AD5310 and is one of a family of pin compatible

• Resolution 10 bits

DACs, including the 8-bit DAC081S101 and the 12-bit

DAC121S101. The DAC101S101 operates over the

• DNL +0.15, -0.05 LSB (typ)

extended industrial temperature range of −40°C to

• Output Settling Time 8 μs (typ)

+105°C while the DAC101S101Q operates over the

• Zero Code Error 3.3 mV (typ)

Grade 1 automotive temperature range of −40°C to

+125°C. The DAC101S101 is available in a 6-lead

• Full-Scale Error −0.06 %FS (typ)

SOT and an 8-lead VSSOP and the DAC101S101Q

• Power Consumption

is availabe in the 6-lead SOT only.

– Normal Mode, 0.63 mW (3.6V) / 1.41 mW

(5.5V) typ

– Pwr Down Mode, 0.14 μW (3.6V) / 0.33 μW

(5.5V) typ

Pin Configuration

Figure 1. Package Number DDC0006A Figure 2. Package Number DGK0008A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 DAC101S101/DAC101S101Q 10-Bit Micro Power, RRO Digital-to-Analog Converter Check for Samples: DAC101S101, DAC101S101-Q1 FEATURES DESCRIPTION • The DAC101S101 is a full-featured, general purpose 10-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to 5.5V supply and consumes just 175 µA of current at 3.6 Volts.
PAGE 2
DAC101S101, DAC101S101-Q1 SNAS321F – JUNE 2005 – REVISED MARCH 2013 www.ti.com Block Diagram VA GND POWER-ON RESET DAC101S101 REF(+) REF(-) DAC REGISTER 10-BIT DAC 10 BUFFER VOUT 10 POWER-DOWN CONTROL LOGIC INPUT CONTROL LOGIC SYNC SCLK 1k 100k DIN PIN DESCRIPTIONS SOT (SOT-23) Pin No. VSSOP Pin No. Symbol 1 4 VOUT DAC Analog Output Voltage. 2 8 GND Ground reference for all on-chip circuitry. 3 1 VA Power supply and Reference input. Should be decoupled to GND.
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DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) Supply Voltage, VA 6.5V −0.3V to (VA + 0.
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DAC101S101, DAC101S101-Q1 SNAS321F – JUNE 2005 – REVISED MARCH 2013 www.ti.com Package Thermal Resistances Package θJA 8-Lead VSSOP 240°C/W 6-Lead SOT 250°C/W Electrical Characteristics The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified.
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DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 Electrical Characteristics (continued) The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified. Symbol Limits (1) Units (Limits) VA = 5V 2.4 V (min) VA = 3V 2.
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DAC101S101, DAC101S101-Q1 SNAS321F – JUNE 2005 – REVISED MARCH 2013 www.ti.com A.C. and Timing Characteristics (continued) The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified.
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DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents, is the power consumed by the device without a load. SETTLING TIME is the time for the output to settle within 1/2 LSB of the final value.
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DAC101S101, DAC101S101-Q1 SNAS321F – JUNE 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated 8 DNL at VA = 3.0V DNL at VA = 5.0V Figure 5. Figure 6. INL at VA = 3.0V INL at VA = 5.0V Figure 7. Figure 8. TUE at VA = 3.0V TUE at VA = 5.0V Figure 9. Figure 10.
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DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated DNL vs. VA INL vs. VA Figure 11. Figure 12. 3V DNL vs. fSCLK 5V DNL vs. fSCLK Figure 13. Figure 14. 3V DNL vs. Clock Duty Cycle 5V DNL vs. Clock Duty Cycle Figure 15. Figure 16.
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DAC101S101, DAC101S101-Q1 SNAS321F – JUNE 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated 10 3V DNL vs. Temperature 5V DNL vs. Temperature Figure 17. Figure 18. 3V INL vs. fSCLK 5V INL vs. fSCLK Figure 19. Figure 20. 3V INL vs. Clock Duty Cycle 5V INL vs. Clock Duty Cycle Figure 21. Figure 22.
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DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated 3V INL vs. Temperature 5V INL vs. Temperature Figure 23. Figure 24. Zero Code Error vs. fSCLK Zero Code Error vs. Clock Duty Cycle Figure 25. Figure 26. Zero Code Error vs. Temperature Full-Scale Error vs. fSCLK Figure 27. Figure 28.
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DAC101S101, DAC101S101-Q1 SNAS321F – JUNE 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated 12 Full-Scale Error vs. Clock Duty Cycle Full-Scale Error vs. Temperature Figure 29. Figure 30. Supply Current vs. VA Supply Current vs. Temperature Figure 31. Figure 32. 5V Glitch Response Power-On Reset Figure 33. Figure 34.
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DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated 3V Wake-Up Time 5V Wake-Up Time Figure 35. Figure 36.
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DAC101S101, DAC101S101-Q1 SNAS321F – JUNE 2005 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION DAC Section The DAC101S101 is fabricated on a CMOS process with an architecture that consists of a resistor string and switches that are followed by an output buffer. The power supply serves as the reference voltage.
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DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register contents) is executed. At this point the SYNC line may be kept low or brought high.
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DAC101S101, DAC101S101-Q1 SNAS321F – JUNE 2005 – REVISED MARCH 2013 www.ti.com Applications Information The simplicity of the DAC101S101 implies ease of use. However, it is important to recognize that any data converter that utilizes its supply voltage as its reference voltage will have essentially zero PSRR (Power Supply Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device.
PAGE 17
DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 Microwire Interface Figure 42 shows an interface between a Microwire compatible device and the DAC101S101. Data is clocked out on the rising edges of the SCLK signal. MICROWIRE DEVICE DAC101S101 CS SYNC SK SCLK SO DIN Figure 42. Microwire Interface USING References as Power Supplies Recall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage.
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DAC101S101, DAC101S101-Q1 SNAS321F – JUNE 2005 – REVISED MARCH 2013 www.ti.com The minimum resistor value in the circuit of Figure 44 should be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the DAC101S101 draws zero current.
PAGE 19
DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 Input Voltage VIN ON / OFF LP2980 VOUT 1 PF DAC101S101 SYNC VOUT = 0V to 5V DIN SCLK Figure 46. Using the LP2980 regulator Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance.
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DAC101S101, DAC101S101-Q1 SNAS321F – JUNE 2005 – REVISED MARCH 2013 www.ti.com Layout, Grounding, and Bypassing For best accuracy and minimum noise, the printed circuit board containing the DAC101S101 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes should be located in the same board layer. There should be a single ground plane.
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DAC101S101, DAC101S101-Q1 www.ti.com SNAS321F – JUNE 2005 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision E (March 2013) to Revision F • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC101S101CIMK/NOPB DAC101S101CIMKX/NOP B DAC101S101CIMM Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC101S101CIMK/NOPB SOT DDC 6 1000 210.0 185.0 35.0 SOT DDC 6 3000 210.0 185.0 35.0 DAC101S101CIMM VSSOP DGK 8 1000 210.0 185.0 35.0 DAC101S101CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 VSSOP DGK 8 3500 367.0 367.0 35.0 SOT DDC 6 1000 210.0 185.0 35.0 SOT DDC 6 3000 210.0 185.0 35.
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