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9.6.8 ARM Memory Wait State Control
9.7 Bandwidth Management
9.7.1 Bus Master DMA Priority Control
www.ti.com Bandwidth Management
The ARM memory wait state control register (ARMWAIT) is used to control ARM926 accesses to its TCM
RAM. At normal ARM operating frequency, a wait state must be inserted when accessing TCM RAM.
When the device is operating at lower speeds, performance may be increased by removing the wait state.
Note that the TCM ROM will always operate with a wait state enabled. See the device-specific data
manual for details on ARMWAIT.
In order to determine allowed connections between masters and slaves, each master request source must
have a unique master ID (mstid) associated with it. The master ID for each DM646x DMSoC master is
shown in Table 9-1 .
Table 9-1. TMS320DM646x DMSoC Master IDs
mstid Master
0 ARM Instruction
1 ARM Data
2 DSP MDMA
3 DSP CFG
4-7 Reserved
8 HDVICP0 CFG
9 HDVICP1 CFG
10 EDMA3 CC TR
11-15 Reserved
16 EDMA3 TC0 read
17 EDMA3 TC0 write
18 EDMA3 TC1 read
19 EDMA3 TC1 write
20 EDMA3 TC2 read
21 EDMA3 TC2 write
22 EDMA3 TC3 read
23 EDMA3 TC3 write
24-31 Reserved
32 PCI
33 HPI
34 ATA
35 EMAC
36 USB
37 VLYNQ
38 VPIF mstr1 read
39 VPIF mstr0 write
40 TSIF0 read
41 TSIF0 write
42 TSIF1 read
43 TSIF1 write
44 VDCE write
45 VDCE read
46-63 Reserved
SPRUEP9A – May 2008 System Control Module 107
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