Datasheet

OUTP9
OUTN9
OUTP8
OUTN8OUTP10
OUTN10
OUTP15
OUTN15
OUTP13
OUTN13
OUTP12
OUTN12
OUTP14
OUTN14
OUTP11
OUTN11
1
JP7JP7
C93
0.1uF
C93
0.1uF
C106
0.1uF
C106
0.1uF
1 2
R94 150R94 150
1
JP13JP13
1 2
R90 150R90 150
1
JP19JP19
1
JP14JP14
2 3
1
4 5
J39
SMA-EDGE
J39
SMA-EDGE
C94
0.1uF
C94
0.1uF
1 2
R91 150R91 150
1 2
R95 150R95 150
1
2
R71
150
R71
150
C107
0.1uF
C107
0.1uF
1 2
R103 150R103 150
2 3
1
4 5
J38
SMA-EDGE
J38
SMA-EDGE
2 3
1
4 5
J33
SMA-EDGE
J33
SMA-EDGE
1
JP15JP15
1
2
R96
150
R96
150
1 2
R92 150R92 150
1
JP4JP4
1 2
R97 150R97 150
1
JP16JP16
1 2
R99 150R99 150
2 3
1
4 5
J32
SMA-EDGE
J32
SMA-EDGE
1 2
R104150R104150
1 2
R93 150R93 150
1
2
R108
150
R108
150
1
JP5JP5
1
JP3JP3
1 2
R98 150R98 150
1
JP17JP17
1 2
R100150R100150
1
2
R109
150
R109
150
1
JP6JP6
1
JP18JP18
Schematics and Layout www.ti.com
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Figure 4. CDCLVP1216EVM—Schematic
6 Low Additive Phase Noise Clock Buffer Evaluation Board SCAU029 – May 2009
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