Datasheet

2
Pinouts
CD54HC533, CD54HCT533
(CERDIP)
CD74HC533, CD74HCT533
(PDIP)
TOP VIEW
CD54HC563
(CERDIP)
CD74HC563, CD74HCT563
(PDIP, SOIC)
TOP VIEW
Functional Block Diagram
HC/HCT533
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
V
CC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
LE 11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
D0
D1
D2
D3
D4
D6
D5
D7
GND
V
CC
Q1
Q2
Q3
Q0
Q4
Q5
Q6
Q7
LE
O
0
D
0
LE
OE
O
1
D
1
O
2
D
2
O
3
D
3
O
4
D
4
O
5
D
5
O
6
D
6
O
7
D
7
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
TRUTH TABLE
OUTPUT ENABLE LATCH ENABLE DATA Q OUTPUT
LHHL
LHLH
LL lH
LLhL
HXXZ
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior to
the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563