Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - multiplexers, demultiplexers TSSOP 16

CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,

www.ti.com

SCHS122J –NOVEMBER 1997–REVISED FEBRUARY 2011

CD74HCT4052, CD54/74HC4053, CD54/74HC54053

HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXERS/DEMULTIPLEXERS

Check for Samples: CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,

FEATURES

– Direct LSTTL Input Logic Compatibility

= 0.8 V Max, V

= 2 V Min

• Wide Analog Input Voltage Range. . ±5 V Max

– CMOS Input Compatibility

• Low ON Resistance

≤ 1 μA at V

, V

– 70 Ω Typical (V

– V

= 4.5 V)

– 40 Ω Typical (V

– V

= 9 V)

DESCRIPTION

• Low Crosstalk Between Switches

These devices are digitally controlled analog switches

• Fast Switching and Propagation Speeds

which utilize silicon gate CMOS technology to

• Break-Before-Make Switching

achieve operating speeds similar to LSTTL with the

low power consumption of standard CMOS integrated

• Wide Operating Temperature Range

circuits.

–55°C to 125°C

These analog multiplexers/demultiplexers control

• CD54HC/CD74HC Types

analog voltages that may vary across the voltage

– Operation Control Voltage . . . . . . 2 V to 6 V

supply range (i.e., V

to V

). They are bidirectional

– Switch Voltage . . . . . . . . . . . . . . 0 V to 10 V

switches thus allowing any analog input to be used as

an output and vice-versa. The switches have low ON

resistance and low OFF leakages. In addition, all

• CD54HCT/CD74HCT Types

three devices have an enable control which, when

– Operation Control Voltage . . . 4.5 V to 5.5 V

high, disables all switches to their OFF state.

– Switch Voltage . . . . . . . . . . . . . . . 0 V to 10

ORDERING INFORMATION

(1)

TEMP. RANGE

PART NUMBER PACKAGE

(°C)

CD54HC4051F3A –55 to 125 16 Ld CERDIP

CD54HC4052F3A –55 to 125 16 Ld CERDIP

CD54HC4053F3A –55 to 125 16 Ld CERDIP

CD54HCT4051F3A –55 to 125 16 Ld CERDIP

CD74HC4051E –55 to 125 16 Ld PDIP

CD74HC4051M –55 to 125 16 Ld SOIC

CD74HC4051MT –55 to 125 16 Ld SOIC

CD74HC4051M96G3 –55 to 125 16 Ld SOIC

CD74HC4051NSR –55 to 125 16 Ld SOP

CD74HC4051PWR –55 to 125 16 Ld TSSOP

CD74HC4051PWT –55 to 125 16 Ld TSSOP

CD74HC4052E –55 to 125 16 Ld PDIP

CD74HC4052M –55 to 125 16 Ld SOIC

CD74HC4052MT –55 to 125 16 Ld SOIC

CD74HC4052M96G3 –55 to 125 16 Ld SOIC

CD74HC4052NSR –55 to 125 16 Ld SOP

CD74HC4052PW –55 to 125 16 Ld TSSOP

CD74HC4052PWR –55 to 125 16 Ld TSSOP

(1) When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of

250.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com CD74HCT4052, CD54/74HC4053, CD54/74HC54053 HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXERS/DEMULTIPLEXERS Check for Samples: CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, FEATURES 1 • • • • • • • • – Direct LSTTL Input Logic Compatibility VIL = 0.8 V Max, VIH = 2 V Min Wide Analog Input Voltage Range. .
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com ORDERING INFORMATION(1) (continued) TEMP.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com FUNCTIONAL DIAGRAM OF HC/HCT4051 CHANNEL IN/OUT VCC A7 A6 A5 A4 A3 A2 A1 A0 16 4 2 5 1 12 15 14 13 TG TG S0 11 TG S1 TG 10 BINARY TO 1 OF 8 DECODER WITH ENABLE LOGIC LEVEL CONVERSION S2 3 A COMMON OUT/IN TG 9 TG TG E 6 TG 8 7 GND VEE Table 1.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com FUNCTIONAL DIAGRAM OF HC4052, CD74HCT4052 A CHANNELS IN/OUT VCC A3 A2 A1 A0 11 15 14 12 16 TG TG TG S1 S0 9 BINARY TO 1 OF 4 DECODER WITH ENABLE LOGIC LEVEL CONVERSION TG 13 COMMON A OUT/IN TG 3 COMMON B OUT/IN 10 TG E 6 TG TG 8 7 1 5 2 4 GND VEE B0 B1 B2 B3 B CHANNELS IN/OUT Table 2.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com FUNCTIONAL DIAGRAM OF 'HC4053, CD74HCT4053 VCC LOGIC LEVEL CONVERSION 16 BINARY TO 1 OF 2 DECODERS WITH ENABLE IN/OUT C1 C0 B1 B0 A1 A0 3 5 1 2 13 12 TG S0 11 S1 10 14 A COMMON OUT/IN 15 B COMMON OUT/IN 4 C COMMON OUT/IN TG TG TG S2 TG 9 TG E 6 8 7 GND VEE Table 3.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC – VEE DC supply voltage –0.5 10.5 V VCC DC supply voltage –0.5 7 V VEE DC supply voltage 0.5 –7 V IIK DC input diode current VI < – 0.5 V or VI > VCC + 0.5 V ±20 mA IOK DC switch diode current VI < VEE – 0.5 V or VI > VCC + 0.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com Recommended Operating Area as a Function of Supply Voltages 8 6 VCC − GND (V) VCC − GND (V) 8 HCT HC 4 2 0 0 2 4 6 8 10 12 6 HCT HC 4 2 0 VCC − VEE (V) 0 −2 −4 −6 −8 VEE − GND (V) Figure 1. Figure 2.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com DC Electrical Specifications (Continued) AMBIENT TEMPERATURE, TA TEST CONDITIONS 25°C PARAMETER VIS (V) VI (V) VEE (V) VCC (V) MIN TYP MAX –40°C to 85°C –55°C to 125°C MIN MIN MAX UNIT MAX HCT Types VIH High-level input voltage 4.5 to 5.5 VIL Low-level input voltage 4.5 to 5.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com Table 4. HCT INPUT LOADING TABLE INPUT UNIT LOADS (1) 4051, 4053 All 0.5 4052 All 0.4 TYPE (1) Unit load is ΔICC limit specified in DC Specifications table, e.g., 360 mA MAX at 25°C.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com Analog Channel Specifications Typical values at TA = 25°C PARAMETER CI TEST CONDITIONS Switch input capacitance CCOM Common output capacitance HC/HCT TYPES fMAX See Figure 3 (1) (2) VCC (V) 4052 12 4053 8 4051 145 –2.25 2.25 200 4051 180 –4.5 4.5 (1) (2) (3) 12 See Figure 7 (2) (3) MHz 185 200 All –2.25 2.25 0.035 All –4.5 4.5 0.018 4051 –2.25 2.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION VCC VCC 0.1µF VI = VIH VOS SWITCH ON VIS 10pF 50Ω SINE− WAVE VIS dB METER 10µF VIS SWITCH ON VOS 10kΩ 50pF VCC /2 VCC /2 fIS = 1kHz TO 10kHz Figure 3. Frequency Response Test Circuit DISTORTION METER Figure 5. Sine-Wave Distortion Test Circuit VCC VIS R 0.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION VCC tr = 6ns tf = 6ns 90% 50% 10% SWITCH INPUT tPLH tPHL VEE 90% 50% 10% SWITCH OUTPUT FIGURE 8A. 6ns 6ns 90% E OR Sn tr 6ns 50% E OR Sn 10% tPLZ tPLZ 10% tPHZ OUTPUT LOW TO OFF tPZH OUTPUT HIGH TO OFF 50% SWITCH OFF SWITCH ON SWITCH ON FIGURE 8B. HC TYPES GND tPZL 50% 10% tPHZ 90% 3V 0.3 GND 50% 6ns 2.7 1.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com TYPICAL PERFORMANCE CURVES 120 0 VCC = 4.5V GND = −4.5V VEE = −4.5V RL = 50Ω PIN 4 TO 3 −2 80 VCC − VEE = 4.5V −4 60 VCC = 2.25V GND = −2.25V VEE = −2.25V RL = 50Ω PIN 4 TO 3 dB ON RESISTANCE (Ω) 100 VCC − VEE = 6V 40 −6 VCC − VEE = 9V 20 −8 1 2 3 4 5 6 INPUT SIGNAL VOLTAGE (V) 7 8 9 Figure 11.
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CD/74HC4051, CD54/74HCT4051, CD54/74HC4052, SCHS122J – NOVEMBER 1997 – REVISED FEBRUARY 2011 www.ti.com TYPICAL PERFORMANCE CURVES 0 VCC = 2.25V GND = −2.25V VEE = −2.25V RL = 50Ω PIN 5 TO 4 −20 dB −40 VCC = 4.5V GND = −4.5V VEE = −4.5V RL = 50Ω PIN 5 TO 4 −60 −80 −100 10K 100K 1M FREQUENCY (Hz) 10M 100M Figure 17.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC4051M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4051M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4051M96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Jan-2014 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC4053M96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4053M96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4053PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 CD74HC4053PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Jan-2014 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4051PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC4051PWR TSSOP PW 16 2000 364.0 364.0 27.0 CD74HC4051PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC4051PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HC4052M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC4052M96 SOIC D 16 2500 364.0 364.0 27.
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