Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver PDIP 20

Data sheet acquired from Harris Semiconductor

SCHS167E

Features

• HC/HCT240 Inverting

• HC/HCT241 Non-Inverting

• HC/HCT244 Non-Inverting

• Typical Propagation Delay = 8ns at V

= 5V,

= 15pF, T

= 25

C for HC240

• Three-State Outputs

• Buffered Inputs

• High-Current Bus Driver Outputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC240 and ’HCT240 are inverting three-state buffers

having two active-low output enables. The CD74HC241,

’HCT241, ’HC244 and ’HCT244 are non-inverting three-

state buffers that differ only in that the 241 has one active-

high and one active-low output enable, and the 244 has two

active-low output enables. All three types have identical

pinouts.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC240F3A -55 to 125 20 Ld CERDIP

CD54HC244F3A -55 to 125 20 Ld CERDIP

CD54HCT240F3A -55 to 125 20 Ld CERDIP

CD54HCT241F3A -55 to 125 20 Ld CERDIP

CD54HCT244F3A -55 to 125 20 Ld CERDIP

CD74HC240E -55 to 125 20 Ld PDIP

CD74HC240M -55 to 125 20 Ld SOIC

CD74HC240M96 -55 to 125 20 Ld SOIC

CD74HC241E -55 to 125 20 Ld PDIP

CD74HC241M -55 to 125 20 Ld SOIC

CD74HC241M96 -55 to 125 20 Ld SOIC

CD74HC244E -55 to 125 20 Ld PDIP

CD74HC244M -55 to 125 20 Ld SOIC

CD74HC244M96 -55 to 125 20 Ld SOIC

CD74HCT240E -55 to 125 20 Ld PDIP

CD74HCT240M -55 to 125 20 Ld SOIC

CD74HCT240M96 -55 to 125 20 Ld SOIC

CD74HCT240PW -55 to 125 20 Ld TSSOP

CD74HCT240PWR -55 to 125 20 Ld TSSOP

CD74HCT240PWT -55 to 125 20 Ld TSSOP

CD74HCT241E -55 to 125 20 Ld PDIP

CD74HCT241M -55 to 125 20 Ld SOIC

CD74HCT241M96 -55 to 125 20 Ld SOIC

CD74HCT244E -55 to 125 20 Ld PDIP

CD74HCT244M -55 to 125 20 Ld SOIC

CD74HCT244M96 -55 to 125 20 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

November 1997 - Revised October 2004

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC240, CD54/74HCT240,

CD74HC241, CD54/74HCT241,

CD54/74HC244, CD54/74HCT244

High-Speed CMOS Logic

Octal Buffer/Line Drivers, Three-State

[ /Title

(CD74

HC240

D74

HCT24

CD74

HC241

D74

HCT24

CD74

HC244

D74

Summary of content (19 pages)

PAGE 1
[ /Title (CD74 HC240 , CD74 HCT24 0, CD74 HC241 , CD74 HCT24 1, CD74 HC244 , CD74 Data sheet acquired from Harris Semiconductor SCHS167E CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 High-Speed CMOS Logic Octal Buffer/Line Drivers, Three-State November 1997 - Revised October 2004 Features Ordering Information • HC/HCT240 Inverting PART NUMBER • HC/HCT241 Non-Inverting TEMP.
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CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Pinout CD54HC240, CD54HCT240, CD54HCT241, CD54HC244, CD54HCT244 (CERDIP) CD74HC240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244 (PDIP, SOIC) CD74HCT240, (PDIP, SOIC, TSSOP) TOP VIEW 240 241 244 1OE 1OE 1 1A0 1A0 2 19 2OE (241) 2OE (240, 244) 2Y3 2Y3 3 18 1Y0 1Y0 1A1 1A1 4 17 2A3 2A3 2Y2 2Y2 5 16 1Y1 1Y1 1A2 1A2 6 15 2A2 2A2 2Y1 2Y1 7 14 1Y2 1Y2 1A3 1A3 8 13 2A1 2A1 2Y0 2Y0 9 12 1Y3
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CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . .
PAGE 4
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -55oC TO 125oC SYMBOL VI (V) MIN TYP MAX MIN MAX MIN MAX UNITS IOZ VIL or VIH - 6 - - ±0.5 - ±0.5 - ±10 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.
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CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Switching Specifications PARAMETER CL = 50pF, Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP 2 - - 100 - - 125 - - 150 ns 4.5 - - 20 - - 25 - - 30 ns CL = 15pF 5 - 8 - - - - - - - ns CL = 50pF 6 - - 17 - - 21 - - 26 ns CL = 50pF 2 - - 110 - - 140 - - 165 ns 4.
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CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP Output Enable and Disable Times tTLH, tTHL CL = 50pF 4.5 - - 30 - - 38 - - 45 ns Output Transition Time tTHL, tTLH CL = 50pF 4.
PAGE 7
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244 Test Circuits and Waveforms OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE (Continued) IC WITH THREESTATE OUTPUT OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 5.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC240M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HC241M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HC244M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC240M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HC241M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HC244M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT240M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT240PWR TSSOP PW 20 2000 367.0 367.0 38.0 CD74HCT240PWT TSSOP PW 20 250 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.