Datasheet

− 8 −
Test Circuits and Waveforms
FIGURE 1. DATA PROPAGATION DELAYS, SET−UP AND HOLD TIMES
FIGURE 2. STROBE PROPAGATION DELAYS AND SET−UP
AND HOLD TIMES
FIGURE 3. ENABLE AND DISABLE TIMES
6ns 6ns
90%
V
S
10%
V
S
t
PLH
V
S
t
PLH
V
S
t
PHL
t
PHL
t
SU
t
H
t
W
t
W
CLOCK
SERIAL IN
Q
n
, QS
1
QS
2
INPUT LEVEL
GND
INPUT LEVEL
GND
V
OH
V
OL
V
OH
V
OL
INPUT LEVEL
GND
INPUT LEVEL
GND
V
OH
V
OL
V
OH
V
OL
V
S
t
PLH,
t
PHL
Q
n
SERIAL IN
CLOCK
STROBE
V
S
V
S
t
SU
t
H
t
W
V
S
OUTPUT
t
r
= 6ns
t
f
= 6ns
OE 90%
V
S
10%
t
PZL
t
PLZ
LOW TO OFF
t
PHZ
t
PZH
V
S
OUTPUT
HIGH TO OFF
V
S
10%
90%
OUTPUTS
CONNECTED
OUTPUTS
CONNECTED
OUTPUTS
DISCONNECTED
CD54/74HC4094, CD74HCT4094